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• 2026-10-20 Bazelizing Third-Party FPGA Designs: Two Case Studies #FPGA#bazel#openxc7

  Converting existing open-source FPGA projects to Bazel and rules_openxc7 makes hardware builds reproducible, eliminates machine-specific paths, and enables one-command bitstream generation without vendor licensing …

• 2026-10-17 Bazelizing a Custom RISC CPU with 4x4 Systolic Matrix Accelerator #FPGA#bazel#openxc7

  Open-source digital signal processing and machine learning accelerators are frequently published as student or research projects. While the RTL architecture is often innovative, the surrounding build and test scaffolding …

• 2026-10-17 Bazelizing mmRISC-2: A Full RISC-V SoC with rules_openxc7 #FPGA#bazel#openxc7

  Converting existing open-source FPGA projects to Bazel and rules_openxc7 transforms fragile, vendor-locked hardware build scripts into reproducible, sandboxed workflows. This case study examines our complete Bazelization …

• 2026-10-15 rules_fusesoc: FuseSoC Cores as Bazel Dependencies #bazel#FPGA#RISC-V

  rules_fusesoc integrates FuseSoC, the FPGA core package manager, into hermetic Bazel builds. Users declare desired core libraries and IP dependencies in Bazel build files. The module resolves dependencies and exports …

• 2026-10-14 First Steps with rules_openxc7: A Beginner’s Guide #bazel#FPGA#openxc7

  This tutorial teaches you how to build your first FPGA bitstream with Bazel and the open-source rules_openxc7 toolchain. You do not need any prior Bazel experience, and you do not need to install AMD Vivado or compile …

• 2026-10-08 Doom on a RISC-V core written in TxHDL #TxHDL#FPGA#RISC-V

  Doom now runs on Vreteno, the RISC-V core written in TxHDL, on an Artix-7 FPGA board. The game draws into a framebuffer in DDR3 memory, the board shows it on HDMI, and the keys come over the serial line. This post shows …

• 2026-10-08 openxc7 or Vivado: Build Times and Results Measured #bazel#FPGA#openxc7

  I built the same three designs with the open toolchain and with Vivado, through the same Bazel rules, and timed every build from cold and warm caches. Small designs build two to three times faster with the open tools. …

• 2026-10-06 Razboj: a minimal GPU in TxHDL #GPU#FPGA#Rust

  Razboj is a minimal graphics rasteriser implemented in approximately one hundred lines of TxHDL. It reads a display list from memory and writes rendered pixels into a framebuffer over an AXI bus. TxHDL lowers the design …

• 2026-10-05 Linux boots to a shell on Vreteno #RISC-V#Linux#FPGA

  Mainline Linux now boots to a shell on Vreteno, the RISC-V core written in TxHDL. It runs on the Alinx AX7A200B board, an Artix-7 FPGA with 1 GiB of DDR3 memory, at 100 MHz. The kernel runs in supervisor mode with …

• 2026-10-04 Thanklessly Maintaining Open Source Software: the book #books#open source#humor

  Thanklessly Maintaining Open Source Software started as a fake O’Reilly book cover, and it is now an actual book on Amazon. It has 95 pages, a year in the life of one unlucky maintainer, and a price of exactly one …

• 2026-10-01 rules_openxc7: Open-Source 7-Series FPGA Toolchains in Bazel #bazel#FPGA#openxc7

  rules_openxc7 brings open-source FPGA synthesis and place-and-route for AMD 7-series chips into Bazel. It drives Yosys, nextpnr-xilinx, Project X-Ray, and openFPGALoader through the same target interface as rules_vivado. …

• 2026-09-29 Vreteno: a RISC-V core written in TxHDL #RISC-V#FPGA#Rust

  Vreteno is a 32-bit RISC-V processor core designed in TxHDL. TxHDL is a hardware description language implemented as a native Rust library. The core implements the RV32IMC instruction set architecture: the base integer …

• 2026-09-29 wdbcvt: Bundling Waveform Test Corpora and Daily Nightly Releases #EDA#Vivado#bazel

  wdbcvt now publishes two new release archives with every build: a documentation bundle and a waveform corpus. The waveform archive packages the test suite’s .wdb files, ground-truth .fst conversions, and HDL source files …

• 2026-09-25 Fuchsia Internals, Vol. II: The Build System and Toolchains #Fuchsia#build systems#GN

  Volume II of the Fuchsia Internals series examines the build system architecture and toolchain infrastructure. The primary complexity in Fuchsia builds stems from the multi-toolchain model. Under this design, the build …

• 2026-09-24 grlib: Gaisler’s GRLIB and the NOEL-V Core as a Bazel Module #bazel#FPGA#RISC-V

  The grlib Bazel module packages GRLIB, Gaisler’s (Frontgrade’s) GPL VHDL IP library, so that the NOEL-V RV64 RISC-V core and the AMBA infrastructure around it can be consumed as ordinary Bazel dependencies. It is the …

• 2026-09-20 An icosahedron on HDMI, drawn by a TxHDL core #TxHDL#FPGA#RISC-V

  tl;dr: A RISC-V core written in TxHDL draws a turning icosahedron on a monitor, with the TxHDL logo in the corner. Watch it at https://youtu.be/YbHtntvvydk. The whole thing, core, memory, video, Ethernet and a serial …

• 2026-09-12 Automated Tests on Simulation Output, with SQLite #EDA#VHDL#Verilog

  This article demonstrates converting a VCD dump into an indexed SQLite database using go-vcd-parser, then using a query language to answer questions about the signals. A logic simulator answers questions about a digital …

• 2026-09-12 TxHDL: a hardware description language is just a Rust async runtime #Rust#FPGA#RISC-V

  TxHDL is an open-source hardware description language embedded directly in Rust as an async runtime library, developed by Dragiša Janković and Filip Filmar (me). Instead of inventing a custom compiler and type checker, …

• 2026-09-04 wdbcvt: reading Vivado’s undocumented .wdb waveform files #EDA#Vivado#FPGA

  wdbcvt is an open-source converter that reads Vivado’s .wdb waveform files and converts them to the open-source FST format. Vivado’s xsim simulator writes simulation waveforms to a proprietary binary format that external …

• 2026-09-03 rules_vivado: FPGA Synthesis and Place-and-Route in Bazel #bazel#FPGA#Vivado

  rules_vivado drives the AMD/Xilinx Vivado FPGA toolchain from Bazel: compile, simulate, synthesize, place-and-route, generate a bitstream, and program the device, all as ordinary build actions instead of clicks in a GUI …

• 2026-08-25 Fuchsia Internals, Vol. I: The Graphics and Display Pipeline #Fuchsia#graphics#Vulkan

  Volume I of the Fuchsia Internals report series examines the graphics and display pipeline. Graphics serves as a comprehensive system application that exercises core kernel primitives simultaneously. Rather than using an …

• 2026-07-25 Fuchsia Internals: A New Report Series for Hardware Engineers #Fuchsia#Zircon#operating systems

  I have written a series of technical reports on the internals of Fuchsia, Google’s capability-based microkernel operating system. The material addresses electrical, register-transfer level (RTL), and FPGA engineers …

• 2026-07-23 The FPGA Hardware Interview: A Topic Guide with Questions and Exercises #FPGA#interviews#VHDL

  Technical interviews for FPGA and digital design engineering positions draw from established digital design principles. Candidates often encounter difficulty communicating solutions under strict time constraints. To …

• 2026-04-11 mkill: a memory watchcat #bazel#go#GCP

  mkill is a Go program that continuously monitors memory usage of the programs owned by the current user. It kills the program with the sharpest rise in memory utilization when the overall system memory occupancy goes …