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Doom on a RISC-V core written in TxHDL

Thu, 08 Oct 2026 00:00:00 +0000

Doom now runs on Vreteno, the RISC-V core written in TxHDL, on an Artix-7 FPGA board. The game draws into a framebuffer in DDR3 memory, the board shows it on HDMI, and the keys come over the serial line. This post shows what runs, how fast, and how the way TxHDL designs are built lets changes like this one go from a plan to the board quickly.

Figure 1: Freedoom's first level, rendered by the same Doom source as the board's, built for the host. The board draws the same frames into its DDR3 framebuffer.

What runs on the board

The board is an Alinx AX7A200B with a Xilinx Artix-7 XC7A200T. The design on it is the TxHDL flagship system:

openxc7 or Vivado: Build Times and Results Measured

Thu, 08 Oct 2026 00:00:00 +0000

I built the same three designs with the open toolchain and with Vivado, through the same Bazel rules, and timed every build from cold and warm caches. Small designs build two to three times faster with the open tools. Sixteen RISC-V cores build faster with Vivado, and Vivado’s circuits use about half the logic. Setting up the measurements turned up five problems, three of them in my own rules.

What was compared

rules_openxc7 and rules_vivado share one target interface: vivado_project, vivado_synthesis and vivado_place_and_route. The first runs Yosys, nextpnr-xilinx and Project X-Ray. The second runs Vivado 2025.2, which Bazel installs from the installer archive on first use. Switching a design between them changes one load line.

Razboj: a minimal GPU in TxHDL

Tue, 06 Oct 2026 00:00:00 +0000

Razboj is a minimal graphics rasteriser implemented in approximately one hundred lines of TxHDL. It reads a display list from memory and writes rendered pixels into a framebuffer over an AXI bus. TxHDL lowers the design to synthesizable Verilog and VHDL, and the build verifies both netlists against the software simulation trace. This post describes the rasteriser architecture and hardware design tradeoffs.

What it draws

The reference demonstration scene measures 64 by 64 pixels (4,096 pixels total). The scene consists of eight display list entries: a background clear, three rectangles, and four triangles. The rasteriser renders the entire scene in approximately 13,000 clock cycles. A verification harness reads the completed framebuffer from memory and saves the output image.

Linux boots to a shell on Vreteno

Mon, 05 Oct 2026 00:00:00 +0000

Mainline Linux now boots to a shell on Vreteno, the RISC-V core written in TxHDL. It runs on the Alinx AX7A200B board, an Artix-7 FPGA with 1 GiB of DDR3 memory, at 100 MHz. The kernel runs in supervisor mode with virtual memory turned on. OpenSBI runs in machine mode below it, and a BusyBox shell runs in user mode above it. This post describes what the core needed for that, how the boot was brought up, and what is still missing.

Thanklessly Maintaining Open Source Software: the book

Sun, 04 Oct 2026 00:00:00 +0000

Thanklessly Maintaining Open Source Software started as a fake O’Reilly book cover, and it is now an actual book on Amazon. It has 95 pages, a year in the life of one unlucky maintainer, and a price of exactly one hexadecimal dollar. This post explains what is in it, and why you might want it anyway.

Buy it on Amazon →

rules_openxc7: Open-Source 7-Series FPGA Toolchains in Bazel

Thu, 01 Oct 2026 00:00:00 +0000

rules_openxc7 brings open-source FPGA synthesis and place-and-route for AMD 7-series chips into Bazel. It drives Yosys, nextpnr-xilinx, Project X-Ray, and openFPGALoader through the same target interface as rules_vivado. This post covers the toolchain architecture, how the rules translate Xilinx constraints, reproducible bitstreams, and how to swap between Vivado and open tooling in one line.

Why open tooling in Bazel

Building for FPGAs usually means one of two extremes. You either install a 100-gigabyte proprietary vendor suite, or you maintain fragile shell scripts around open-source tools. rules_openxc7 avoids both problems.

Vreteno: a RISC-V core written in TxHDL

Tue, 29 Sep 2026 00:00:00 +0000

Vreteno is a 32-bit RISC-V processor core designed in TxHDL. TxHDL is a hardware description language implemented as a native Rust library. The core implements the RV32IMC instruction set architecture: the base integer set, standard multiply/divide extensions, and compressed instructions. It supports traps, hardware interrupts, and system memory access via an AXI bus. Lockstep verification checks core state against a reference model on every cycle, while gate-level netlists match cycle-accurate Rust simulations. This article details the core microarchitecture, verification strategy, and FPGA implementation.

wdbcvt: Bundling Waveform Test Corpora and Daily Nightly Releases

Tue, 29 Sep 2026 00:00:00 +0000

wdbcvt now publishes two new release archives with every build: a documentation bundle and a waveform corpus. The waveform archive packages the test suite’s .wdb files, ground-truth .fst conversions, and HDL source files together. Nightly builds now run daily, check the repository forge for new commits, and publish all build artifacts to Forgejo and GitHub.

Why a standalone waveform corpus matters

Tool developers who study Vivado’s .wdb format need test cases. Vivado is a multi-gigabyte software package. Running simulations requires licenses and tool setups that many open-source developers do not maintain. The wdbcvt repository already contains dozens of simulated test cases across VHDL, Verilog, and SystemVerilog. Previously, these test cases stayed inside the repository tree alongside intermediate simulation files. Developers of external tools had to clone the full repository or run Vivado locally to obtain sample waveforms.

Fuchsia Internals, Vol. II: The Build System and Toolchains

Fri, 25 Sep 2026 00:00:00 +0000

Volume II of the Fuchsia Internals series examines the build system architecture and toolchain infrastructure. The primary complexity in Fuchsia builds stems from the multi-toolchain model. Under this design, the build system compiles a single source target across multiple toolchain contexts, producing distinct binary artifacts for each execution environment. A link to the full report appears below.

Note on these reports: These reports were compiled automatically. Verify specific implementation details against upstream source code before relying on them.

grlib: Gaisler's GRLIB and the NOEL-V Core as a Bazel Module

Thu, 24 Sep 2026 00:00:00 +0000

The grlib Bazel module packages GRLIB, Gaisler’s (Frontgrade’s) GPL VHDL IP library, so that the NOEL-V RV64 RISC-V core and the AMBA infrastructure around it can be consumed as ordinary Bazel dependencies. It is the module that puts the CPU into Cocoapuffs, the SoC that boots Fuchsia’s Zircon kernel on an Artix-7 FPGA. It is also the module where I learned the most about what it costs to move a large, make-era VHDL codebase into a modern build system, which is what this post is mostly about. It follows rules_vivado in my series on the modules behind cocoapuffs-fpga.

An icosahedron on HDMI, drawn by a TxHDL core

Sun, 20 Sep 2026 00:00:00 +0000

tl;dr: A RISC-V core written in TxHDL draws a turning icosahedron on a monitor, with the TxHDL logo in the corner. Watch it at https://youtu.be/YbHtntvvydk. The whole thing, core, memory, video, Ethernet and a serial loader, is one bitstream in the board’s flash, and the program that draws is 560 lines of Rust that go down the serial port in about a second. Read on for how it is put together.

What you are looking at

The board is an Alinx AX7A200B, with an Artix-7 200T on it. The core is Vreteno, an RV32IMC that I wrote in TxHDL together with Dragiša Janković. If you have not seen TxHDL before: you write the hardware as a Rust program, and the Verilog, the simulation and the checks all fall out of a Rust library and a few macros. I wrote a whole post about it if you want the long version.

Automated Tests on Simulation Output, with SQLite

Sat, 12 Sep 2026 00:00:00 +0000

This article demonstrates converting a VCD dump into an indexed SQLite database using go-vcd-parser, then using a query language to answer questions about the signals. A logic simulator answers questions about a digital design. Typically, it answers them in a graphical waveform viewer, requiring an engineer to inspect transitions on a screen. Automating these checks in continuous integration requires translating waveform traces into machine-readable data.

Inside SQLite, engineers write Go tests to assert timing properties, such as validating that reset deasserts at 10 ns or verifying a 200 MHz clock. These checks execute automatically and fail the build whenever an assertion violates.

TxHDL: a hardware description language is just a Rust async runtime

Sat, 12 Sep 2026 00:00:00 +0000

TxHDL is an open-source hardware description language embedded directly in Rust as an async runtime library, developed by Dragiša Janković and Filip Filmar (me). Instead of inventing a custom compiler and type checker, TxHDL expresses digital circuits using standard Rust types, structs, and asynchronous functions. From a single Rust source file, the library provides software simulation, Verilog and VHDL code generation, and multi-tool verification. To demonstrate hardware fidelity, the project includes Vreteno, a 32-bit RISC-V CPU core written in TxHDL and running on an Artix-7 FPGA at 100 MHz. Since then, the same library has been used to write a minimal GPU, an AXI bus, a network on chip, an Ethernet MAC and an HDMI output, each with its own document. Each of these designs will get a post of its own here later.

wdbcvt: reading Vivado's undocumented .wdb waveform files

Fri, 04 Sep 2026 00:00:00 +0000

wdbcvt is an open-source converter that reads Vivado’s .wdb waveform files and converts them to the open-source FST format. Vivado’s xsim simulator writes simulation waveforms to a proprietary binary format that external tools cannot open. wdbcvt parses these .wdb files and produces standard FST waveforms that open directly in GTKWave and Surfer. The tool converts real simulations, including a dual-core RISC-V SoC with 5,696 signals and 18,875,466 value changes in 71 seconds. Below are downloads, usage instructions, and sample waveform images.

rules_vivado: FPGA Synthesis and Place-and-Route in Bazel

Thu, 03 Sep 2026 00:00:00 +0000

rules_vivado drives the AMD/Xilinx Vivado FPGA toolchain from Bazel: compile, simulate, synthesize, place-and-route, generate a bitstream, and program the device, all as ordinary build actions instead of clicks in a GUI or a pile of ad-hoc TCL. This post kicks off a series on the Bazel modules behind cocoapuffs-fpga, the SoC repo from the Zircon-on-FPGA bring-up. I have covered some modules before (rules_ghdl, rules_shar, fshlib, bazel-ebook, and build-in-docker); the coming posts cover the rest: this one, then grlib, rules_fusesoc, rules_vunit, rules_dtc, vhdl_ls_gen, OpenSBI, and rules_osvvm.

My homelab is fully ephemeral

Sun, 30 Aug 2026 00:00:00 +0000

In my homelab, no individual server is treated as irreplaceable. Every machine across the laboratory (build nodes, developer workstations, and continuous integration runners) is fully ephemeral: it can be terminated at any moment, by choice or provider eviction, and reconstituted from scratch in minutes. The only state that persists is committed source code in git and backups distributed across three isolated storage domains. This article outlines the architecture of this environment and the operational tenets behind it.

Fuchsia Internals, Vol. I: The Graphics and Display Pipeline

Tue, 25 Aug 2026 00:00:00 +0000

Volume I of the Fuchsia Internals report series examines the graphics and display pipeline. Graphics serves as a comprehensive system application that exercises core kernel primitives simultaneously. Rather than using an in-kernel DRM/KMS subsystem, Fuchsia divides display responsibilities among cooperating user-space services. These services communicate across FIDL channels using zero-copy shared VMOs. A link to the full report appears below.

Note on these reports: These reports were compiled automatically. Verify specific implementation details against upstream source code before relying on them.

Bazel all the way down: how I build programmable hardware

Mon, 17 Aug 2026 00:00:00 +0000

This is a description of how I build programmable hardware. Everything that goes into Cocoapuffs (my RISC-V system-on-chip on an Artix-7 FPGA), including the RTL, firmware, simulations, synthesis, bitstream, and board programming, comes out of a single bazel build on a machine that has nothing installed on it but bazel. The build is hermetic, ephemeral, and reproducible, and it behaves identically whether it runs on my laptop, on a virtual machine in the cloud, or in continuous integration. Below is why I do it this way, what the approach looks like, and which Bazel rules do the heavy lifting.

Fuchsia Internals: A New Report Series for Hardware Engineers

Sat, 25 Jul 2026 00:00:00 +0000

I have written a series of technical reports on the internals of Fuchsia, Google’s capability-based microkernel operating system. The material addresses electrical, register-transfer level (RTL), and FPGA engineers rather than kernel developers. This article introduces the publication series, which covers the reports progressively. The complete collection spans fourteen reference volumes. The overview document is linked at the end of this article, and each subsequent post will provide the full text and download link for an individual volume.

The FPGA Hardware Interview: A Topic Guide with Questions and Exercises

Thu, 23 Jul 2026 00:00:00 +0000

Technical interviews for FPGA and digital design engineering positions draw from established digital design principles. Candidates often encounter difficulty communicating solutions under strict time constraints. To assist engineers preparing for technical interviews, this guide provides a structured 29-page review titled “The FPGA Hardware Interview.” The document pairs topic reviews with realistic interview questions, model responses, and dual-language coding exercises in both VHDL and SystemVerilog. A link to the full document appears below.

Booting Fuchsia's Zircon on a homebrew RISC-V SoC, on an Artix-7 FPGA

Sun, 19 Jul 2026 00:00:00 +0000

Fuchsia’s Zircon kernel now boots on Cocoapuffs, my homebrew RISC-V system-on-chip on an AMD Artix-7 FPGA. As far as I know, this is the first Fuchsia boot on programmable hardware. Below you will find the boot video and the full chain, from a SERV serial loader through OpenSBI to userspace. All of the code, from RTL to the boot chain, lives in filmil/cocoapuffs-fpga. The rest of this post chronicles the five bugs that stood in the way.

Announcing bazel_local_nix 0.1.0

Thu, 28 May 2026 00:00:00 +0000

I’m excited to announce the release of bazel_local_nix 0.1.0!

bazel_local_nix provides Bazel rules that make Nix packages available inside a Bazel workspace without a host-level Nix installation and without nix-portable.

What’s New?

Earlier versions of this project relied on shimming Bazel through a nix-portable nix-shell wrapper. That approach has been completely removed and replaced by a more robust rule set.

The new rules bootstrap an ephemeral Nix from the official binary release, run it unprivileged inside a bwrap (bubblewrap) user namespace against a persistent store, and expose the results as ordinary Bazel artifacts.

Respin: upspin revival

Sun, 19 Apr 2026 00:00:00 +0000

tl;dr: I revived the upspin project source code. See it at https://github.com/filmil/upspin, and https://github.com/filmil/upspin-gdrive. Since April, it has also gained post-quantum encryption, streaming of large files, a writable keyserver, and a lot of automated checking. Read on to learn what that actually means.

Updated on 2026-10-10. The first version of this article described the revival as of April 2026. This version adds what changed since, in What happened since and How it is checked now, and updates the list of what is still missing.

Synod: Paxos agent

Sat, 18 Apr 2026 00:00:00 +0000

Synod is a distributed Paxos coordination agent implemented in Go. It manages a highly available, synchronized Key-Value store across a network of peers using the Paxos consensus algorithm. It allows multiple dynamically joining network nodes to agree on a shared state, ensuring fault tolerance and consistency across the cell. Find it at: https://github.com/filmil/synod

Quickstart

This quickstart shows how to download the repository and quickly start 3 synod agents which talk to each other and are already set up to work properly. It establishes state directories for each agent following the XDG base directory specification.

mkill: a memory watchcat

Sat, 11 Apr 2026 00:00:00 +0000

mkill is a Go program that continuously monitors memory usage of the programs owned by the current user. It kills the program with the sharpest rise in memory utilization when the overall system memory occupancy goes beyond the user-configured kill threshold. Download a binary release, or see the source code on Github.

I created mkill because I am handling some programs which tend to run away with memory use, in a setup which can not be easily sandboxed. It prevents killing a random process, which then usually ends up killing my remote session on a GCP virtual machine, messing up the ongoing user workloads. Hence, a monitor program. TUI because I often use text-only sessions.

Inventory of programmable hardware tooling

Sun, 01 Feb 2026 00:00:00 +0000

A link page of interesting libraries and utilities I found.

Libraries, utilities, etc.

My stuff

All available at: https://hdlfactory.com/bazel-registry/ if you are willing to use bazel.

https://github.com/filmil/bazel_rules_nvc, builds NVC from source, fully hermetic.
https://github.com/filmil/bazel_rules_ghdl, uses prebuilt GHDL, fully hermetic.
https://github.com/filmil/bazel_rules_vivado, uses a prebuilt dockerized Vivado
Fusesoc / edalize: https://github.com/filmil/bazel_rules_fusesoc_2, builds a hermetic fusesoc/edalize distribution from Python source.
https://github.com/filmil/bazel_nvc_osvvm
https://github.com/filmil/bazel_rules_vunit
https://github.com/filmil/bazel_nvc_vivado

fshlib: shell library

Sat, 03 Jan 2026 00:00:00 +0000

fshlib

fshlib is a simple shell library for logging. It provides a set of functions to log messages with different severity levels.

Github repo: https://github.com/filmil/fshlib

Usage

To use the library, source the log.bash file in your script:

source "path/to/log.bash"

Then you can use the logging functions:

log::info "This is an info message"
log::warn "This is a warning message"
log::error "This is an error message"

Functions

log::info: Logs an informational message.
log::warn: Logs a warning message.
log::error: Logs an error message.
log::debug: Logs a debug message. This message is only shown if the DEBUG environment variable is set to true or log.
log::prefix: Prefixes each line of the input with a given string.

Example

#!/usr/bin/env bash

source "path/to/log.bash"

log::info "Starting the script"
log::warn "Something might be wrong"
log::error "Something went wrong"

echo "some output" | log::prefix "[my-prefix] "

note to self: do not remove `.bazelversion`

Sat, 20 Dec 2025 00:00:00 +0000

note to self: do not remove `.bazelversion` from projects

The other day, I was pondering whether to keep setting particular bazel version in projects. I even removed some, to see what would become of it.

Since I use the bazelisk installation method, I get automatic bazel updates when a new version is released.

It turns out that this remains a bad idea. An auto-update to bazel 8.5.0 caused some of my CI workflows to fail, likely because bazel 8.5.0 requires some updates to tools versions as well.

rules_shar: bazel rules for creating self-extracting archives (shars)

Sat, 22 Nov 2025 00:00:00 +0000

This repository provides Bazel rules for creating self-extracting archives (“shar"s) out of shell binaries.

See section “what is this” below for details.

Details at: https://github.com/filmil/rules_shar

Usage

To use the rules, add the following to your MODULE.bazel file:

bazel_dep(name = "rules_shar", version = "0.0.0") # Select your version, of course.

Then, in your BUILD.bazel file, you can use the shar_binary rule to create a self-extracting archive, as a drop-in replacement for the rule sh_binary.

Hermetic, Ephemeral, Reproducible Builds: Take Three (3)

Wed, 29 Oct 2025 00:00:00 +0000

Bazel rules to support a debian rootfs

The idea of this repository is to provide a hermetic, ephemeral and reproducible repository of prebuilt binaries, which can then be brought into bazel builds to remove the dependence on local binary installations.

Find the project page at: https://github.com/filmil/bazel_debian_rootfs

This is otherwise a difficult task. Making a hermetic bazel build involves painstakingly bringing in each needed binary one at a time. Often, this means descending into the rats nest of dependencies and having to bring them all in. One can convince themselves that this approach is then equivalent to rebuilding an entire software repository from scratch. Something that we should avoid doing if we can help it. And something that presents a significant barrier to entry for bazel builds, and one that is best avoided if possible.

Hermetic, Ephemeral, Reproducible Builds: Take Three (2)

Wed, 15 Oct 2025 00:00:00 +0000

This is another piece of news in my quest for hermetic, ephemeral, and reproducible builds (“HER”).

If you read my articles in the past months or so, you may have noticed that I am looking for good ways of creating completely hermetic, ephemeral, reproducible, but also practical builds.

Issues to solve

The following is a list of issues with my previous HER build approaches:

I do not want to manage a software repository. I think that instead I should be able to reuse an already worked out solution wholesale. Ideally, bringing an existing software repository would be the way to go. The “N+B” approach did this, but even ephemeral nix installation ended up being somewhat invasive, as it required a special installation step which could fail in hard to track down ways.

Bazel knowledge sources

Tue, 07 Oct 2025 00:00:00 +0000

This is a collection of links to interesting articles and knowledge sources about the Bazel build system that I found.

I’m motivated to do this after spending considerable time developing a thing that already existed. Just because I was not following the “right” communities I basically wasted a lot of effort reinventing a wheel. Useful wheel, but reinventing nevertheless.

I plan to update the sources once in a while, as I discover things.

Hermetic, Ephemeral, Reproducible Builds: Take Three (1)

Mon, 06 Oct 2025 00:00:00 +0000

This is another piece of news in my quest for hermetic, ephemeral, and reproducible builds (“HER”).

If you read my articles in the past months or so, you may have noticed that I am looking for good ways of creating completely hermetic, ephemeral, reproducible, but also practical builds.

In the past, I offered two approaches to HER builds that I believe take a stab at providing HER properties, while also remaining practical to everyday build engineers. I’ll discuss them below, as well as a proposal for improving them.

Getting ready for the brave new Bazel Modules world

Mon, 29 Sep 2025 00:00:00 +0000

Update 2025-10-19: I made a searchable index of modules available from my registry at https://www.hdlfactory.com/bazel-registry.

As Bazel 9.0 promises to disable the old dependency management approaches based on WORKSPACE by the end of 2025, I figured we should better start preparing. This is my preparation central.

Bazel modules promise to usher the era of trivial bazel dependency management. However, getting from here to there seems to be a journey fraught with peril. Migration guides are few and far between. And it’s never about the easy stuff what makes it fraught, it’s always the side quests and corner cases that create issues. Keep your knowledge base handy.

lit2md: a literate program converter from code to Markdown

Sun, 21 Sep 2025 00:00:00 +0000

lit2md: a literate program converter from code to Markdown

lit2md is a simplistic literate programming (LP) converter.

See at: https://github.com/filmil/lit2md

It takes a source code file annotated with special “literate” programming comments, and outputs a markdown file in which the literate programming comments are converted into markdown text, and code is converted into code blocks.

Example

For example, consider the simplistic hello.cc

//] # An example Hello World program.
//]
//] Don't forget headers!
#include <iostream>

//] And now, the rest of the code here:
int main() {
		std::cout << "Hello world" << std::endl;
		exit(0);
}

Running:

Writing XDC Clock Constraints for Vivado

Mon, 01 Sep 2025 00:00:00 +0000

Writing XDC Clock Constraints for Vivado

This guide explains how to properly constrain a digital design with multiple clocks in an XDC (Xilinx Design Constraints) file, specifically for use in Vivado batch mode. We’ll cover primary clocks, generated clocks, and the relationships between them.

The Foundation: Primary Clocks

A primary clock is a clock that enters the FPGA from an external source. It’s the root of a clock tree. You must define all primary clocks first.

Decentralized Downloads for Bazel: Introducing `bazel_rules_bt`

Fri, 01 Aug 2025 00:00:00 +0000

Decentralized Downloads for Bazel: Introducing `bazel_rules_bt`

In the world of reproducible builds and efficient dependency management, Bazel stands out as a powerful tool. However, fetching large or uncommon dependencies can sometimes be a bottleneck. Enter bazel_rules_bt, a set of Bazel rules that uses the BitTorrent protocol to bring decentralized file downloading capabilities directly into your build system.

Find the project page at https://github.com/filmil/bazel_rules_bt

The Power of Peer-to-Peer for Builds

bazel_rules_bt addresses a common challenge: efficiently acquiring external files and archives that might be hosted on less reliable servers, or when you want to take advantage of peer-to-peer distribution for speed and resilience. By integrating the BitTorrent protocol, this extension offers a robust and potentially faster alternative to traditional HTTP/S downloads, especially for widely available public data or large files.

Mastering Resolved Signals in VHDL: A Comprehensive Guide for Digital Design

Mon, 14 Jul 2025 00:00:00 +0000

I asked Gemini to teach me about the VHDL resolved signals. What you read below is the result.

Mastering Resolved Signals in VHDL: A Comprehensive Guide for Digital Design

1. Introduction to Signals in VHDL

The Fundamental Role of Signals in Hardware Description

In VHDL, signals serve as the foundational elements for representing physical wires and interconnections within a digital circuit. They are paramount in describing hardware behavior because, unlike variables, signals inherently possess a time dimension. This means that their values are not updated instantaneously but rather after a specified delay, which can be a default delta delay (an infinitesimal simulation time step) or an explicitly defined inertial or transport delay.¹ This characteristic is vital for accurately modeling the concurrent and time-dependent nature of real-world hardware operations.

How to shoot yourself in the foot with inout signals

Mon, 07 Jul 2025 00:00:00 +0000

How to shoot yourself in the foot with inout signals

They say that no good deed goes unpunished. Here’s an example of a footgun in VHDL which stems from in my view an eminently reasonable desire to keep the entity interface definitions compact.

When defining entities in VHDL, I try to keep the entity definition compact and keep the rate of mistakes low by grouping individual signals into records, so that they could be manipulated as a unit. For example you would have a package definition that defines a record like so (library use declarations omitted for brevity):

VHDL IEEE Libraries and Numeric Type Conversion: A Definitive Reference

Sun, 29 Jun 2025 00:00:00 +0000

I asked Gemini to teach me the VHDL type conversions. What you read below is the result. An annoying generated podcast will be available for a while.

VHDL IEEE Libraries and Numeric Type Conversions: A Definitive Reference

Introduction

The VHSIC Hardware Description Language (VHDL) is a formal, strongly-typed language engineered for use in all phases of the creation of electronic systems, including development, verification, synthesis, and testing.¹ Its dual nature, being both human-readable and machine-readable, underpins its role in communicating, maintaining, and procuring hardware designs.³ The core language, while powerful, is intentionally minimal. Its true utility in modern digital design is unlocked through a suite of standardized packages governed by the Institute of Electrical and Electronics Engineers (IEEE). These libraries extend VHDL’s capabilities, providing the essential types and functions needed to model complex hardware phenomena accurately and efficiently.

Packaging AMD Xilinx Vivado ML Standard edition 2025.1 in a Docker container

Thu, 19 Jun 2025 00:00:00 +0000

I updated the repository https://github.com/filmil/vivado-docker/ with the changes required to package Vivado 2025.1. As of this writing, version 2025.1 is the last published version. I hope that the updated version will remove some of the bugs I discovered in the previous version I dockerized, which was 2023.2.

I use the container built from this repository as the basis for my vivado tooling for bazel. While this was the primary reason for making this dockerization recipe, the result is also usable as a stand-alone and ephemeral installation of Vivado.

`rules_nixpkgs` use

Fri, 11 Apr 2025 00:00:00 +0000

`rules_nixpkgs` use

This is a run-down of tips and tricks for the use of rules_nixpkgs, a rule set for bringing in nix packages for use in bazel.

I got involved with the use of rules_nixpkgs as a result of my work on hermetic, ephemeral and reproducible builds. My additions to the process are in the repository bazel_local_nix, which allows an ephemeral nix installation, only in service of the current bazel compilation.

Per-project `.bazelrc` settings

Here’s the .bazelrc file I place in the root directory of my projects:

Bazel rules for "build-in-docker" (or "bid")

Tue, 11 Feb 2025 00:00:00 +0000

Bid allows you to create a build rule that runs a single bazel build action inside a Docker container. And if you can run a single action, you can run more if you so choose. This helps you if you must use software which is hard to bazelize, such as typically some EDA packages.

The limitation is, you must have a way to invoke docker run. I can afford to do that, but depending on your setup you might not. Not everyone is happy to run arbitrary binaries through a daemon that runs as root by default (it seems that rootless docker, or podman, are not compatible with use in bazel, so that avenue seems closed for the foreseeable future).

Typeset your own ebooks easily with `bazel-ebook`

Tue, 04 Feb 2025 00:00:00 +0000

Other formats:

Original content is at: https://github.com/filmil/bazel-ebook
The rendered HTML edition at: https://hdlfactory.com/bazel_ebook_html/

Introduction

This repository is a set of bazel build rules that allow you to write a moderately complex book in the Markdown text format, and produce EPUB and Kindle’s MOBI formats from them. You can also produce a PDF format book, which allows you to preview the results slightly more convenient than by reading the resulting books.

The documentation is available in the following formats:

Using `glbl.v` module in a Verilog simulation in Vivado

Sat, 16 Nov 2024 00:00:00 +0000

A quick note about correct use of glbl.v in a Verilog simulation in Vivado. This note is way less confusing than any notes you may find elsewhere on the Internet.

glbl.v is a small collection of “global” signals that are being referred to in Vivado’s simulation sources for primitive elements in AMD (fka Xilinx) devices, such as OSERDES2 and others. This file gets included automatically in simulation setups if you use the Vivado GUI.

go-vcd-parser: a tested VCD parser and toolkit in Go

Sat, 26 Oct 2024 00:00:00 +0000

go-vcd-parser reads Value Change Dump (VCD) files, the waveform format that simulators such as Verilator, Icarus Verilog and nvc write. The format is defined in IEEE 1800. The parser handles the 4-value format and the pragmatic extensions that real simulators produce.

Why another VCD parser

Most open source VCD parsers are written in Python, Perl or C++, and most ship with few tests or none. Some throw an exception on the first realistic file. go-vcd-parser is written in Go, compiles to a static binary, and a test suite guards its behavior: unit tests for individual VCD stanzas, unit tests for odd snippets found in the wild, and integration tests over complete files sampled from actual simulator runs.

GNOME tips and tricks

Tue, 22 Oct 2024 00:00:00 +0000

Reusing the general approach from this post gives a way for setting Shift_L+Shift_R as layout change:

$ gsettings set org.gnome.desktop.wm.keybindings switch-input-source "['<Shift>Shift_L']"
$ gsettings set org.gnome.desktop.wm.keybindings switch-input-source-backward "['<Shift>Shift_R']"

This can not be done from the GNOME settings UI. It also works only accidentally, since it is not possible to be very intentional about left and right Shift modifier in the shortcut key definitions. Whew.

How to use $readmemh correctly

Mon, 07 Oct 2024 00:00:00 +0000

What?

$readmemh is a Verilog directive that allows you to initialize an array.

It works differently in simulation compared to synthesis. In simulation, this directive behaves as a “read file into array”. In synthesis, this directive behaves as a repository of initial values for, say, block RAM.

While the purpose of the directive is documented every which way, the correct usage of the directive is woefully under-explained.

How to use it correctly

If you have a file in a directory say:

From zero to RISC-V in hardware, in 6 minutes

Sat, 05 Oct 2024 00:00:00 +0000

From zero to RISC-V in hardware, in 6 minutes

Program your FPGA with a one-liner command. It’s a kind of magic.

This is a project in sustainable FPGA development that I have been working on. It ties together several smaller projects that I developed in a perpetual quest for hermetic, ephemeral, and reproducible builds. As far as I know, you can not find any setup like this anywhere else. It is a long and non-eventual video, but hardware people should be able to recognize the appeal.

nix requires `ranlib`

Sat, 14 Sep 2024 00:00:00 +0000

Be forewarned: HER builds with nix require a functional `ranlib`

This is something seldom known, and a very sharp corner to cut yourself on. But you really want to know if you are using nix.

I lost an entire day trying to figure out mysterious “symbol not found” errors while trying to link a hermetic instance of the nvc VHDL compiler under bazel with rules_foreign_cc, in a HER build, when using link-time optimizations (“LTO”), which is the norm these days.

`bazel` rules for GHDL

Tue, 03 Sep 2024 00:00:00 +0000

`bazel` rules for GHDL

I present to you https://github.com/filmil/bazel_rules_ghdl: a set of bazel rules for converting VHDL into Verilog.

This for example allows running VHDL code in a Verilator simulation. Commercial tools usually do not care what HDL the modules are written in. But usually commercial tools are the final mile in open source HDL development.

Before you get there, you want the ability to run reasonably detailed simulations.

What?

This repository contains a bazel rule set for running ghdl, the VHDL simulator and synthesizer, specifically to convert VHDL designs into Verilog.

`bazel` rules for a riscv64 bare metal rust compiler

Sat, 31 Aug 2024 00:00:00 +0000

`bazel` rules for a riscv64 bare metal rust compiler

This article assumes that you have bazel installed via the bazelisk method.

This is the latest example in my repository at: https://github.com/filmil/bazel-experiments

The subdirectory https://github.com/filmil/bazel-experiments/tree/main/riscv64-rust-baremetal shows how to build a bare-metal binary for 64-bit RISC-V, using bazel and a hermetic Rust compiler.

It leans onto the set of bazel bare metal rules for 64-bit RISC-V, since the Rust compiler uses GNU ld for its linker. Unfortnately, the know-how for building the toolchain has been lost to time it seems. I might need to find a way to rebuild this from scratch, possibly using the instructions from here and here

`bazel` installation via the `bazelisk` method

Sat, 24 Aug 2024 00:00:00 +0000

`bazel` installation via the `bazelisk` method

Here is how I install bazel. I use this installation method on all of my machines. I do not think it is practical to go about this any other way. It is implied in all of my writings about bazel.

Why?

Sadly, bazel versions are wildly incompatible between major version releases. This means that as you encounter projects using newer and newer bazel versions, you may encounter random compatibility issues.

`bazel` rules for a riscv64 bare metal GCC compiler

Sat, 17 Aug 2024 00:00:00 +0000

`bazel` rules for a riscv64 bare metal GCC compiler

The repository https://github.com/filmil/bazel_rules_gcc_riscv64_baremetal contains bazel rules that can be used for a hermetic bare metal GCC cross-compiler for a 64-bit RISC-V machine, running in M-mode.

It is based on the toolchain for the muntjac processor. Based on the lowRISC toolchains repo at: https://github.com/lowRISC/lowrisc-toolchains, and some custom patches.

`lazygit` tips and tricks

Mon, 12 Aug 2024 00:00:00 +0000

`lazygit` tips and tricks

These are some tips and tricks for lazygit that I keep forgetting how to do.

Split a commit into multiple commits

Based on the discussion here.

Open lazygit
4 to move to the commits panel
Enter key to select a commit to split
Use regular commands to stage and unstage parts you need.
Ctrl-P n to select “move to new commit”.
Write the commit message. Ctrl-O does not seem to work, so I usually put an arbitrary but memorable blurb, and reword the commit later.

The new commit will be put as a child of the one you just split.

Remote programming of an AMD (fka Xilinx) Artix-7 device

Mon, 08 Jul 2024 00:00:00 +0000

Summary

Here is how you can set up a hardware server (hw_server) in AMD Vivado 2023.2.

Once you do this, that you can move your workbench to a virtual machine in your cloud of choice - mine is GCP - but program a device which is attached to a machine that’s close to you.

The FPGA device in question is an AMD Artix-7 A200T. I suspect any other device supported by Vivado will work too. This is a much more advanced setup than what is described on the AMD help site. That setup assumes a local server, a local hardware attachment point, and it does no authentication. In contrast, this setup uses ssh tunneling to set up a secure connection between the workbench machine and the programming host, so that it can be used between any two machines on the Internet so long as they can see each other via a TCP connection.

PSA: Google Nest Router can serve as an Access Point

Sat, 25 May 2024 00:00:00 +0000

Google Nest Router (2nd Generation) can serve as an access point

I accidentally bought the Google Nest 2nd Generation Router when I needed an Access Point.

It turns out that the Router can act as an Access Point and join a mesh network that already has an active Router. Just select “Access Point” when setting it up instead of “Router”.

This is very useful in multiple ways:

If you accidentally buy the wrong device;
If you don’t want the microphone that’s built into the Access Point.
If you want the ability to plug into an Ethernet point on the Access Point. (Since actual Access Points don’t have an Ethernet port, and the Router has two).

Hermetic, ephemeral, reproducible builds ('her')

Wed, 01 May 2024 00:00:00 +0000

Summary

This short note defines the notions of hermetic, ephemeral and reproducible software build, as used in my writing.

I call this “her” for short.

Hermetic

A build is said to be hermetic, if each build step only has access to the set of input artifacts that are minimally required for the build to succeed.

Hermeticity is useful to ensure build correctness – as it allows us to confirm that each build dependency step is well captured, and that none are omitted.

Why do I bother with `bazel`?

Sat, 27 Apr 2024 00:00:00 +0000

Summary

I bother with bazel.

Here is why.

Background

Bazel is a build system. Originally created at Google for internal purposes, then eventually open sourced. Since then, it has not been universally accepted. You can find discussions where bazel is being put down in favor of other build systems.

Yet, I have been using bazel in a lot of my recent projects, and have been quite pleased with the results. I intend to explain here why this works for me. I do not intend to compare to anything else, if that is what you are after, you will need to look for that elsewhere.

Nix+Bazel = ❤️

Sat, 20 Apr 2024 00:00:00 +0000

You, too, can have a fully hermetic, reproducible, and ephemeral bazel build.

If you are in a hurry, fast forward to https://github.com/filmil/bazel_local_nix

Intro

While looking for non-invasive and reproducible ways to create my dev environment, I considered bazel. I wrote up some of the results of this search.

I like bazel because not only will it build my project reproducibly, but will also set up the development environment for doing so beforehand. It means that I only need to have bazel installed on the local machine, and clone the repository I need, and I have all that is required to build and test the cloned code. This is in big contrast to the more “conventional” approaches to building, where you are left to work out how to pick and install the correct versions of the dependencies your code needs to build.

`docker` tips and tricks

Thu, 15 Feb 2024 00:00:00 +0000

Docker tips and tricks

Save an image to an archive

docker save imagename | gzip > myimage.tar.gz

Load image to an archive

docker load < myimage.tar.gz

bazel does not like FIFOs

Mon, 05 Feb 2024 00:00:00 +0000

Bazel does not like FIFOs

Perhaps obvious in retrospect, but it is not possible for a bazel build artifact to generate a named pipe in the filesystem.

The after-step checks will object if an output directory contains at least one.

I am not sure if this is accidental or not, but it kind of makes sense, since FIFOs are not hermetic, just as network connections are not hermetic.

You can see the error message that one of my build rules hit when attempting to create a FIFO.

Unix domain sockets in go

Sat, 06 Jan 2024 00:00:00 +0000

After a lengthy search I found the below article that explains the use of Unix domain sockets in go:

https://johnrefior.com/gobits/read/go-introduction-to-unix-socket-communication

Running docker containers in Synology NAS

Mon, 01 Jan 2024 00:00:00 +0000

If this advice helped you, let me know.

How to run docker containers under Synology NAS, easily and with custom settings

Prompted by a recent need to run a local Jupyter instance using the Jupyter Docker Stacks.

The easiest way to run docker containers under Synology NAS is to use the Container Manager, which is available through Synology’s Package Center right from the user interface.

The Container Manager allows you to run custom containers and set some, but not all, options. I found various attempts at this, but none are simple, and some are quite elaborate, such as installing Portainer, which is a whole other and separate can of worms. Not to mention that it’s also vying for the not that much memory of your NAS.

TIM-011 video playlist

Mon, 25 Dec 2023 00:00:00 +0000

TIM-011 video playlist

TIM-011 was an 8-bit teaching computer that was ostensibly developed by IMP in what is now Serbia.

Here is a public collection of videos related to the TIM-011 computer. Most of the videos, and especially the more impressive ones, are by other people. Please see individual videos for authorship information.

TIM-011 gets a unit test library

Sun, 24 Dec 2023 00:00:00 +0000

TIM-011 was an 8-bit teaching computer that was ostensibly developed by IMP in what is now Serbia.

It is hard to develop for any machine without a way to test quickly whether your work results in something usable. Since it takes quite a while to spin up a TIM-011 emulator and run things on it, it was not going to be practical to wait for all the slow machinery to get spun up.

bazoekt: easy code indexing and search for your Bazel projects

Sun, 17 Dec 2023 00:00:00 +0000

Update 2026-04-17: Bazoekt has been modernized and revived. Sourcegraph has taken over maintenance of zoekt, but what they actually did was disable the old repo and dismantle the zoekt infrastructure, so it couldn’t be compiled. I took over the old version of zoekt, spruced it up so that it builds again, and put it up at https://github.com/filmil/zoekt. Then revived bazoekt on top of that, see it at: https://github.com/filmil/bazoekt

Since I can’t remember anything these days, I often find myself sifting through my code looking for specific keywords. Sometimes grep isn’t quite enough, and something more is needed.

bazel: excavating an unknown file from a `foreign_cc` rule

Thu, 14 Dec 2023 00:00:00 +0000

Excavating an unknown file from a `foreign_cc` rule

I discovered this trick recently, while trying (and mostly failing) to build a library.

I discovered that it is possible to excavate an arbitrary file from the resulting directory by using the gen_dir file group, then copying out the needed file using genrule.

Entire BUILD.bazel:

load("@rules_foreign_cc//foreign_cc:defs.bzl", "make")
filegroup(
    name = "all_files",
    srcs = glob(["**"]),
)
make(
  name = "lib",
  targets = [
		" -C $BUILD_TMPDIR" +
		" BIN_DIR=$$INSTALLDIR$$/lib" +
        " ROOT=$BUILD_TMPDIR" +
		" EXT_BUILD_ROOT=$EXT_BUILD_ROOT" +
		" CC=$EXT_BUILD_ROOT/$SDCC" +
		" AS=$EXT_BUILD_ROOT/$SDAS" +
		" AR=$EXT_BUILD_ROOT/$SDAR" +
		" CPP=$EXT_BUILD_ROOT/$SDCPP" +
		" LD=$EXT_BUILD_ROOT/$SDLD" +
		" ISET=-mz180" +
		" all",
  ],
  env = {
    "CFLAGS": "",
    "CXXFLAGS": "",
    "AR_FLAGS": "",
    "ARFLAGS": "",
    "LDFLAGS": "",
	"SDCC": "$(location @sdcc-linux//:sdcc)",
	"SDAS": "$(location @sdcc-linux//:sdas)",
	"SDAR": "$(location @sdcc-linux//:sdar)",
	"SDCPP": "$(location @sdcc-linux//:sdcpp)",
	"SDLD": "$(location @sdcc-linux//:sdld)",
  },
  install_prefix = "_install",
  lib_source = ":all_files",
  out_static_libs = [ 
		  "libcpm3-z80.lib",
		  "libsdcc-z80.lib",
  ],
  visibility = ["//visibility:public"],
  build_data = [
		"@sdcc-linux//:sdar",
		"@sdcc-linux//:sdas",
		"@sdcc-linux//:sdcc",
		"@sdcc-linux//:sdcpp",
		"@sdcc-linux//:sdld",
  ]
)

# Excavates the entire resulting directory.
filegroup(
	name = "_crt0_priv",
	srcs = [":lib" ],
	# This is the main point. Then the genrule below
	output_group = "gen_dir",
)

# Excavate a single file by copying it out of the `gen_dir`:
genrule(
	name = "libcpm3",
	srcs = [":_crt0_priv" ],
	outs = ["libcpm3-z80.lib"],
	cmd = "cp $</lib/libcpm3-z80.lib $@",
	visibility = ["//visibility:public"],
)

genrule(
	name = "libsdcc",
	srcs = [":_crt0_priv" ],
	outs = ["libsdcc-z80.lib"],
	cmd = "cp $</lib/libsdcc-z80.lib $@",
	visibility = ["//visibility:public"],
)

genrule(
		name = "crt0",
		srcs = [ ":_crt0_priv"],
		outs = [ "crt0cpm3-z80.rel"],
		cmd = "cp $</lib/crt0cpm3-z80.rel $@",
		visibility = ["//visibility:public"],
)

TIM-011 gets a C runtime library

Wed, 13 Dec 2023 00:00:00 +0000

TIM-011 gets a C runtime library

TIM-011 was an 8-bit teaching computer that was ostensibly developed by IMP in what is now Serbia.

Now that https://github.com/filmil/tim011-tools/issues/3 has been fixed, the TIM-011 tools compile and run with a real C runtime library, thanks to the libcpm-z80 library.

It wasn’t easy to get it to compile with bazel, but after plenty of trial and error I managed to pinpoint the correct incantation. I also ended up with a pull request to libcpm-z80 which contains the generalizations needed to get it to compile under bazel.

TIM-011 computer - how we did things back then

Sun, 03 Dec 2023 00:00:00 +0000

I was a bit hard pressed to find all the proper work attribution. Please let me know if you have data to contribute.

TIM-011

TIM-011 was an 8-bit teaching computer that was ostensibly developed by IMP in what is now Serbia.

It was one of the machines that kick-started my career as a software engineer. For better or worse.

There are precious few resource links for TIM-011, a machine that I personally hold in high regard because of its sentimental value to me. Which is why I set out to collect the resources about TIM-011 and try to preserve them as much as possible. I understand that about 50% of the software that was made available to the original TIM-011 was preserved. The rest was lost to time. It is still theoretically possible to port CP/M software to TIM-011 again (grease and elbows, people!), but the original software is lost.

Packaging AMD Xilinx Vivado ML Standard edition in a Docker container

Mon, 20 Nov 2023 00:00:00 +0000

A while back I wanted to make a hermetic environment for repeatably running Docker tooling.

The results are here: https://github.com/filmil/vivado-docker/

At this time, it’s only able to run the GUI version of the tool. I intend to make it run specific tools when they are needed.

Neovim tips and tricks

Mon, 18 Sep 2023 00:00:00 +0000

From VimScript into Lua

This is my cheat sheet for migrating VimScript into Lua. Things I often forget. There are places to learn about Lua use in Neovim . But, for some reason, I could not find side-by-side examples of VimScript vs Lua for quick migration. So I decided to start my own.

VimScript	Lua
`:nmap abc :something`	`vim.keymap.add({'n'}, 'abc', ':something)`, `noremap` will be with more in the first `{}`
`let g:session_autosave = 'yes'`	`vim.g.session_autosave = 'yes'`
`autocmd BufWrite *py :call DeleteTrailingWs()`	`vim.api.nvim_create_autocmd({'BufWrite'}, {pattern={'*.py'}, command = ":call DeleteTrailingWs()"})`
`let splitbelow = 1`	`vim.opt.splitbelow = true`
`(any vimscript commands)`	`vim.api.nvim_exec2([[ (any vimscript commands) ]])`
`" comment`	`-- comment` (oh, well)

Replacing tabs with spaces

I keep forgetting this: how to set tabstop at 4, and use spaces not tabs to space.

`git` tips and tricks

Sat, 05 Aug 2023 00:00:00 +0000

Often needed little bits of git knowledge that I tend to forget.

Check out the contents of a GitHub PR

From: https://devopscube.com/checkout-git-pull-request/

git fetch origin pull/15/head:test-branch

This will fetch the PR number 15 from GitHub, and have it available in the local branch test-branch.

`bazel` tips and tricks

Sun, 30 Jul 2023 00:00:00 +0000

Often needed little bits of bazel knowledge that I tend to forget.

Module extensions

Reminder about module extensions.

# Also instead of `http.bzl`, `git.bzl` etc.
http_file = use_repo_rule("@bazel_tools//tools/build_defs/repo:http.bzl", "http_file")
http_file(
    name = "data_file",
    url = "http://example.com/file",
    sha256 = "e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855",
)

Print errors inline

By default bazel prints the path to error logs. In development it is often more useful to see the error printed right away.

bazel test --test_output=errors //...

You can add:

test --test_output=errors

into your $HOME/.bazelrc as well.

Print only errors

By default bazel prints the status of passing tests. This causes bazel to print details about failing tests only.

Build a `python` web app in `bazel`

Tue, 25 Jul 2023 00:00:00 +0000

Here is an example python Flask app built with Bazel. See README.md for instructions.

Running the app will start a local dev server for Flask and you should be able to direct your browser at it and see the result. Based on various bits and pieces from the internet on how to do this correctly.

It uses a hermetic python interpreter, which a great improvement for reproducibility over using the local python interpreter.

Tesla ownership experiences so far

Fri, 30 Jun 2023 00:00:00 +0000

We recently became Tesla owners, as our old car unexpectedly gave out. We were expecting to get at least 1 more year out of it. But it was not meant to be.

Now that we’re obnoxious Tesla owners, it is only fair that I bother you with some Electric vehicle ownership experience writeup, for what we figured out so far.

Including arbitrary files into `cc_library` rule in `bazel`

Fri, 23 Jun 2023 00:00:00 +0000

Update 2023-08-17: This is now a feature in bazel, see https://github.com/bazelbuild/bazel/issues/18766 for details. It is available starting bazel version 6.3.0. Use additional_compiler_input parameter to cc_library and other C++ rules to provide arbitrary files.

Adapted from the bazel-discuss mailing list.

I have a cc_library.

I want to set “-fsanitize-ignorelist” to point to a file in my repo.

E.g., I have:
foo.cc
BUILD.bazel
ignorelist.txt
and in BUILD.bazel:
cc_library(
  name = "foo",
  copts = ["-fsanitize-ignorelist=" <TODO what goes here?>],
  srcs = ["foo.cpp"],
)
I’ve tried setting ignorelist.txt as a data dependency, and then referring to it with $(location), but that doesn’t work. I get: clang: error: no such file or directory: ‘bazel-out/k8-fastbuild/ignorelist.txt’

How to use the `make` rule from `rules_foreign_cc` repository for `bazel`

Tue, 13 Jun 2023 00:00:00 +0000

Summary

The bazel build system has rules available to build C or C++ code from external repositories that use other more “conventional” build tools. By this I mean the usual suspects: GNU autotools, GNU make and cmake.

This rules repository is called rules_foreign_cc. While it is somewhat documented, and even has examples, both leave a lot to be desired.

I think it would be really helpful to have at least some sort of a guide for how exactly they work, so that we can use them more effectively. Such a guide, however, does not seem to exist. At least, I was not able to find one.

Home on HDL Factory Home

Doom on a RISC-V core written in TxHDL

What runs on the board

openxc7 or Vivado: Build Times and Results Measured

What was compared

Razboj: a minimal GPU in TxHDL

What it draws

Linux boots to a shell on Vreteno

Thanklessly Maintaining Open Source Software: the book

rules_openxc7: Open-Source 7-Series FPGA Toolchains in Bazel

Why open tooling in Bazel

Vreteno: a RISC-V core written in TxHDL

wdbcvt: Bundling Waveform Test Corpora and Daily Nightly Releases

Why a standalone waveform corpus matters

Fuchsia Internals, Vol. II: The Build System and Toolchains

grlib: Gaisler's GRLIB and the NOEL-V Core as a Bazel Module

An icosahedron on HDMI, drawn by a TxHDL core

What you are looking at

Automated Tests on Simulation Output, with SQLite

TxHDL: a hardware description language is just a Rust async runtime

wdbcvt: reading Vivado's undocumented .wdb waveform files

rules_vivado: FPGA Synthesis and Place-and-Route in Bazel

My homelab is fully ephemeral

Fuchsia Internals, Vol. I: The Graphics and Display Pipeline

Bazel all the way down: how I build programmable hardware

Fuchsia Internals: A New Report Series for Hardware Engineers

The FPGA Hardware Interview: A Topic Guide with Questions and Exercises

Booting Fuchsia's Zircon on a homebrew RISC-V SoC, on an Artix-7 FPGA

Announcing bazel_local_nix 0.1.0

What’s New?

Respin: upspin revival

Synod: Paxos agent

Quickstart

mkill: a memory watchcat

Inventory of programmable hardware tooling

Libraries, utilities, etc.

My stuff

fshlib: shell library

fshlib

Usage

Functions

Example

note to self: do not remove `.bazelversion`

note to self: do not remove .bazelversion from projects

rules_shar: bazel rules for creating self-extracting archives (shars)

Usage

Hermetic, Ephemeral, Reproducible Builds: Take Three (3)

Bazel rules to support a debian rootfs

Hermetic, Ephemeral, Reproducible Builds: Take Three (2)

Issues to solve

Bazel knowledge sources

Hermetic, Ephemeral, Reproducible Builds: Take Three (1)

Getting ready for the brave new Bazel Modules world

lit2md: a literate program converter from code to Markdown

lit2md: a literate program converter from code to Markdown

Example

Writing XDC Clock Constraints for Vivado

Writing XDC Clock Constraints for Vivado

The Foundation: Primary Clocks

Decentralized Downloads for Bazel: Introducing `bazel_rules_bt`

Decentralized Downloads for Bazel: Introducing bazel_rules_bt

The Power of Peer-to-Peer for Builds

Mastering Resolved Signals in VHDL: A Comprehensive Guide for Digital Design

Mastering Resolved Signals in VHDL: A Comprehensive Guide for Digital Design

1. Introduction to Signals in VHDL

The Fundamental Role of Signals in Hardware Description

How to shoot yourself in the foot with inout signals

How to shoot yourself in the foot with inout signals

VHDL IEEE Libraries and Numeric Type Conversion: A Definitive Reference

VHDL IEEE Libraries and Numeric Type Conversions: A Definitive Reference

Introduction

Packaging AMD Xilinx Vivado ML Standard edition 2025.1 in a Docker container

`rules_nixpkgs` use

rules_nixpkgs use

Per-project .bazelrc settings

Bazel rules for "build-in-docker" (or "bid")

Typeset your own ebooks easily with `bazel-ebook`

Introduction

Using `glbl.v` module in a Verilog simulation in Vivado

go-vcd-parser: a tested VCD parser and toolkit in Go

note to self: do not remove `.bazelversion` from projects

Decentralized Downloads for Bazel: Introducing `bazel_rules_bt`

`rules_nixpkgs` use

Per-project `.bazelrc` settings

Be forewarned: HER builds with nix require a functional `ranlib`

`bazel` rules for GHDL

`bazel` rules for a riscv64 bare metal rust compiler

`bazel` installation via the `bazelisk` method

`bazel` rules for a riscv64 bare metal GCC compiler

`lazygit` tips and tricks

Excavating an unknown file from a `foreign_cc` rule