Rust

• 2026-10-08 Doom on a RISC-V core written in TxHDL #TxHDL#FPGA#RISC-V

  Doom now runs on Vreteno, the RISC-V core written in TxHDL, on an Artix-7 FPGA board. The game draws into a framebuffer in DDR3 memory, the board shows it on HDMI, and the keys come over the serial line. This post shows …

• 2026-10-06 Razboj: a minimal GPU in TxHDL #GPU#FPGA#Rust

  Razboj is a minimal graphics rasteriser implemented in approximately one hundred lines of TxHDL. It reads a display list from memory and writes rendered pixels into a framebuffer over an AXI bus. TxHDL lowers the design …

• 2026-09-29 Vreteno: a RISC-V core written in TxHDL #RISC-V#FPGA#Rust

  Vreteno is a 32-bit RISC-V processor core designed in TxHDL. TxHDL is a hardware description language implemented as a native Rust library. The core implements the RV32IMC instruction set architecture: the base integer …

• 2026-09-20 An icosahedron on HDMI, drawn by a TxHDL core #TxHDL#FPGA#RISC-V

  tl;dr: A RISC-V core written in TxHDL draws a turning icosahedron on a monitor, with the TxHDL logo in the corner. Watch it at https://youtu.be/YbHtntvvydk. The whole thing, core, memory, video, Ethernet and a serial …

• 2026-09-12 TxHDL: a hardware description language is just a Rust async runtime #Rust#FPGA#RISC-V

  TxHDL is an open-source hardware description language embedded directly in Rust as an async runtime library, developed by Dragiša Janković and Filip Filmar (me). Instead of inventing a custom compiler and type checker, …

• 2024-08-31 bazel rules for a riscv64 bare metal rust compiler #Rust#bazel#RISC-V

  bazel rules for a riscv64 bare metal rust compiler This article assumes that you have bazel installed via the bazelisk method. This is the latest example in my repository at: https://github.com/filmil/bazel-experiments …