FPGA

• 2026-10-08 Doom on a RISC-V core written in TxHDL #TxHDL#FPGA#RISC-V

  Doom now runs on Vreteno, the RISC-V core written in TxHDL, on an Artix-7 FPGA board. The game draws into a framebuffer in DDR3 memory, the board shows it on HDMI, and the keys come over the serial line. This post shows …

• 2026-10-08 openxc7 or Vivado: Build Times and Results Measured #bazel#FPGA#openxc7

  I built the same three designs with the open toolchain and with Vivado, through the same Bazel rules, and timed every build from cold and warm caches. Small designs build two to three times faster with the open tools. …

• 2026-10-06 Razboj: a minimal GPU in TxHDL #GPU#FPGA#Rust

  Razboj is a minimal graphics rasteriser implemented in approximately one hundred lines of TxHDL. It reads a display list from memory and writes rendered pixels into a framebuffer over an AXI bus. TxHDL lowers the design …

• 2026-10-05 Linux boots to a shell on Vreteno #RISC-V#Linux#FPGA

  Mainline Linux now boots to a shell on Vreteno, the RISC-V core written in TxHDL. It runs on the Alinx AX7A200B board, an Artix-7 FPGA with 1 GiB of DDR3 memory, at 100 MHz. The kernel runs in supervisor mode with …

• 2026-10-01 rules_openxc7: Open-Source 7-Series FPGA Toolchains in Bazel #bazel#FPGA#openxc7

  rules_openxc7 brings open-source FPGA synthesis and place-and-route for AMD 7-series chips into Bazel. It drives Yosys, nextpnr-xilinx, Project X-Ray, and openFPGALoader through the same target interface as rules_vivado. …

• 2026-09-29 Vreteno: a RISC-V core written in TxHDL #RISC-V#FPGA#Rust

  Vreteno is a 32-bit RISC-V processor core designed in TxHDL. TxHDL is a hardware description language implemented as a native Rust library. The core implements the RV32IMC instruction set architecture: the base integer …

• 2026-09-24 grlib: Gaisler’s GRLIB and the NOEL-V Core as a Bazel Module #bazel#FPGA#RISC-V

  The grlib Bazel module packages GRLIB, Gaisler’s (Frontgrade’s) GPL VHDL IP library, so that the NOEL-V RV64 RISC-V core and the AMBA infrastructure around it can be consumed as ordinary Bazel dependencies. It is the …

• 2026-09-20 An icosahedron on HDMI, drawn by a TxHDL core #TxHDL#FPGA#RISC-V

  tl;dr: A RISC-V core written in TxHDL draws a turning icosahedron on a monitor, with the TxHDL logo in the corner. Watch it at https://youtu.be/YbHtntvvydk. The whole thing, core, memory, video, Ethernet and a serial …

• 2026-09-12 TxHDL: a hardware description language is just a Rust async runtime #Rust#FPGA#RISC-V

  TxHDL is an open-source hardware description language embedded directly in Rust as an async runtime library, developed by Dragiša Janković and Filip Filmar (me). Instead of inventing a custom compiler and type checker, …

• 2026-09-04 wdbcvt: reading Vivado’s undocumented .wdb waveform files #EDA#Vivado#FPGA

  wdbcvt is an open-source converter that reads Vivado’s .wdb waveform files and converts them to the open-source FST format. Vivado’s xsim simulator writes simulation waveforms to a proprietary binary format that external …

• 2026-09-03 rules_vivado: FPGA Synthesis and Place-and-Route in Bazel #bazel#FPGA#Vivado

  rules_vivado drives the AMD/Xilinx Vivado FPGA toolchain from Bazel: compile, simulate, synthesize, place-and-route, generate a bitstream, and program the device, all as ordinary build actions instead of clicks in a GUI …

• 2026-08-17 Bazel all the way down: how I build programmable hardware #bazel#FPGA#HER

  This is a description of how I build programmable hardware. Everything that goes into Cocoapuffs (my RISC-V system-on-chip on an Artix-7 FPGA), including the RTL, firmware, simulations, synthesis, bitstream, and board …

• 2026-07-25 Fuchsia Internals: A New Report Series for Hardware Engineers #Fuchsia#Zircon#operating systems

  I have written a series of technical reports on the internals of Fuchsia, Google’s capability-based microkernel operating system. The material addresses electrical, register-transfer level (RTL), and FPGA engineers …

• 2026-07-23 The FPGA Hardware Interview: A Topic Guide with Questions and Exercises #FPGA#interviews#VHDL

  Technical interviews for FPGA and digital design engineering positions draw from established digital design principles. Candidates often encounter difficulty communicating solutions under strict time constraints. To …

• 2026-07-19 Booting Fuchsia’s Zircon on a homebrew RISC-V SoC, on an Artix-7 FPGA #FPGA#RISC-V#Zircon

  Fuchsia’s Zircon kernel now boots on Cocoapuffs, my homebrew RISC-V system-on-chip on an AMD Artix-7 FPGA. As far as I know, this is the first Fuchsia boot on programmable hardware. Below you will find the boot video and …

• 2026-02-01 Inventory of programmable hardware tooling #bazel#FPGA#Vivado

  A link page of interesting libraries and utilities I found. Libraries, utilities, etc. https://registry.bazel.build/modules/rules_verilator https://github.com/lromor/fpga-assembler …

• 2025-09-01 Writing XDC Clock Constraints for Vivado #FPGA#Vivado#EDA

  Writing XDC Clock Constraints for Vivado This guide explains how to properly constrain a digital design with multiple clocks in an XDC (Xilinx Design Constraints) file, specifically for use in Vivado batch mode. We’ll …

• 2025-07-14 Mastering Resolved Signals in VHDL: A Comprehensive Guide for Digital Design #EDA#VHDL#FPGA

  I asked Gemini to teach me about the VHDL resolved signals. What you read below is the result. Mastering Resolved Signals in VHDL: A Comprehensive Guide for Digital Design 1. Introduction to Signals in VHDL The …

• 2025-07-07 How to shoot yourself in the foot with inout signals #EDA#VHDL#FPGA

  How to shoot yourself in the foot with inout signals They say that no good deed goes unpunished. Here’s an example of a footgun in VHDL which stems from in my view an eminently reasonable desire to keep the entity …

• 2025-06-29 VHDL IEEE Libraries and Numeric Type Conversion: A Definitive Reference #EDA#VHDL#FPGA

  I asked Gemini to teach me the VHDL type conversions. What you read below is the result. An annoying generated podcast will be available for a while. VHDL IEEE Libraries and Numeric Type Conversions: A Definitive …

• 2025-06-19 Packaging AMD Xilinx Vivado ML Standard edition 2025.1 in a Docker container #Xilinx#FPGA#Docker

  I updated the repository https://github.com/filmil/vivado-docker/ with the changes required to package Vivado 2025.1. As of this writing, version 2025.1 is the last published version. I hope that the updated version will …

• 2024-11-16 Using glbl.v module in a Verilog simulation in Vivado #FPGA#Vivado#Xilinx

  A quick note about correct use of glbl.v in a Verilog simulation in Vivado. This note is way less confusing than any notes you may find elsewhere on the Internet. glbl.v is a small collection of “global” signals that are …

• 2024-10-26 go-vcd-parser: a tested VCD parser and toolkit in Go #EDA#Verilog#VHDL

  go-vcd-parser reads Value Change Dump (VCD) files, the waveform format that simulators such as Verilator, Icarus Verilog and nvc write. The format is defined in IEEE 1800. The parser handles the 4-value format and the …

• 2024-10-07 How to use $readmemh correctly #FPGA#Verilog

  What? $readmemh is a Verilog directive that allows you to initialize an array. It works differently in simulation compared to synthesis. In simulation, this directive behaves as a “read file into array”. In synthesis, …

• 2024-10-05 From zero to RISC-V in hardware, in 6 minutes #FPGA#bazel#Xilinx

  From zero to RISC-V in hardware, in 6 minutes Program your FPGA with a one-liner command. It’s a kind of magic. This is a project in sustainable FPGA development that I have been working on. It ties together several …

• 2024-07-08 Remote programming of an AMD (fka Xilinx) Artix-7 device #FPGA#Vivado#Xilinx

  Summary Here is how you can set up a hardware server (hw_server) in AMD Vivado 2023.2. Once you do this, that you can move your workbench to a virtual machine in your cloud of choice - mine is GCP - but program a device …

• 2023-11-20 Packaging AMD Xilinx Vivado ML Standard edition in a Docker container #Xilinx#FPGA#Docker

  A while back I wanted to make a hermetic environment for repeatably running Docker tooling. The results are here: https://github.com/filmil/vivado-docker/ At this time, it’s only able to run the GUI version of the tool. …