The FPGA Hardware Interview: A Topic Guide with Questions and Exercises

July 23, 2026

Interviews for FPGA and digital-design roles draw from a stable, well-defined body of knowledge, yet candidates routinely stumble on it because the questions are asked crisply and must be answered under pressure. I am publishing a preparation guide for exactly that situation: a 29-page report, “The FPGA Hardware Interview”, organized as a sequence of topic reviews, each followed by interview-style questions with model answers and, for the design topics, coding exercises solved in both VHDL and SystemVerilog. The PDF is linked below.

A caveat, up front: this report is auto-generated, so take the specifics with a grain of salt. In my reading it holds up well and reads as generally correct, but verify anything you plan to say in an actual interview.

What is inside

The guide opens with how FPGA interviews actually work: the shape of the process, what is tested at each level of seniority, and the single most important preparation (practicing answers out loud). From there it walks the canon in twenty sections:

  • Fundamentals. Digital logic essentials; number representation and arithmetic (two’s complement, fixed point, overflow); sequential logic and finite-state machines, including the classic “1011” sequence-detector exercise.
  • Timing. Static timing analysis (setup, hold, slack, skew, and why the clock period does not appear in the hold check); metastability, synchronizers, and clock-domain crossing; clocking and reset, with a reset-synchronizer exercise.
  • The platform and the languages. FPGA architecture; Verilog and SystemVerilog essentials; VHDL essentials, each with the common pitfalls interviewers like to probe.
  • Design practice. A catalogue of RTL coding idioms; memory and FIFO design; pipelining, latency, and throughput; interfaces and handshake protocols (valid/ready and friends).
  • The rest of the job. Verification and testbenches; debug, bring-up, and timing closure.
  • The endgame. Classic whiteboard problems with full solutions, a rapid-fire question bank for last-minute review, guidance on behavioral and experience questions, and a concrete study plan with further reading.

Every design topic is worked in both HDLs. That is deliberate: interviews rarely let you pick your language, and seeing the same FIFO or synchronizer expressed twice teaches the semantics better than either version alone.

Why publish this

Regular readers know this blog spends most of its time building FPGA systems and the Bazel machinery around them. Interview preparation is the same material viewed under a time limit: if you can explain a CDC synchronizer, a hold check, or a skid buffer clearly in five minutes, you understand it. The guide is written so that a prepared candidate walks in able to answer the expected questions fluently, and to reason aloud through the unexpected ones.

Get the guide

If you find an error, or an interview question you think the guide should cover, let me know.