TxHDL

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  RISC-V Architectural Conformance of the Vreteno Core

  The official RISC-V tests, run on the core's netlist every day

  by Filip Filmar

  This report runs RISC-V International’s architectural tests on Vreteno. The Sail reference model computes the result each test must reproduce, and each test runs on the core’s Verilog netlist under Verilator.

  In the first run, 155 of the 156 tests that apply to the core passed. The one failure found a real defect: the core cannot set mstatus.TVM. The report is rebuilt every day against the newest commit of TxHDL, so the latest copy always describes the core as it is now.

  Read the latest report PDF Source and past reports

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  TxHDL: A Hardware Description Language That Is a Rust Library

  The language, its runtime, and the Vreteno core built with it

  by Filip Filmar and Dragiša Janković

  TxHDL is a hardware description language with no grammar of its own. A design is a Rust program: a unit is a struct, its behaviour is an async fn that waits for clock edges, and the same source simulates, writes a waveform, and lowers to Verilog and VHDL.

  The paper presents the system as it stands and its results. Its largest design is Vreteno, a three-stage RV32IMAC core with Sv32 paging, which runs on an Artix-7 board.

  Read it on the web PDF Source

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  TxHDL

  Hardware in Rust, from Code to Silicon

  by Filip Filmar and Dragiša Janković

  TxHDL is a hardware description language that is a Rust library: a design is async Rust, where waiting for a clock edge is an .await and a transaction is a send on a channel. The book teaches it to hardware engineers who know Verilog or VHDL and to Rust programmers new to hardware, from a blinking LED through simulation, lowering to Verilog and VHDL, and formal checks. It ends with Vreteno, a RISC-V core written in TxHDL, running on an Artix-7 board and taken through an open ASIC flow.

  Planned for 1 December 2026, in paperback and as an ebook. The language itself is on GitHub.

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