TxHDL is a hardware description language with no grammar of its own. A design is a Rust program: a unit is a struct, its behaviour is an async fn that waits for clock edges, and the same source simulates, writes a waveform, and lowers to Verilog and VHDL.

The paper presents the system as it stands and its results. Its largest design is Vreteno, a three-stage RV32IMAC core with Sv32 paging, which runs on an Artix-7 board.