HDL Factory

HDL Factory helps engineering teams build FPGA, RISC-V, and board designs with the same reproducibility and test automation as software. We put vendor EDA tools, simulators, firmware, and PCB flows into one hermetic Bazel build graph.

What We Do

Hermetic EDA and Bazel Builds

Move synthesis, place-and-route, simulation, and firmware into one hermetic Bazel build graph with remote caching and pinned toolchains.

#bazel #vivado #openxc7 #nix

FPGA, RISC-V, and RTL Design

Board bring-up, custom IP cores, RISC-V SoC integration, and cycle-exact FPGA simulation for Linux and Fuchsia targets.

#risc-v #txhdl #fpga #firesim

Verification and Hardware CI

Automated testbenches, waveform pipelines, and continuous integration that run on every pull request.

#vhdl #systemverilog #testing #ci

Hardware Design as Code (CAD)

Schematics in Python, routed PCBs checked by DRC and netlist parity tests, parametric enclosures, and byte-reproducible factory packages.

#kicad#skidl#build123d#step

Recent Factory Floor Notes

2026-11-02 You Deserve Nice Circuit Diagrams: Blockpic Draws Your Netlist #FPGA #bazel #openxc7

“You deserve nice circuit diagrams!” Every digital design document needs pictures. A clean block diagram communicates dataflow, bus widths, and control hierarchy in seconds. Reading through hundreds of lines of RTL or …

2026-10-31 Linux on a Simulated Rocket Core, over Ethernet #FireSim #Linux #RISC-V

Linux 6.18 now boots on FireSim’s Rocket design on an Alinx AX7A200B board. The host reaches the board over an Ethernet cable, as in the last post. The whole run takes 4 min 36 s: 4 min 22 s to load the software, and 13 …

2026-10-30 filmil’s Auto Reload: a tab reloader with two permissions #Chrome #browser extension #security

filmil’s Auto Reload is a Chrome extension that reloads a tab every few seconds, minutes or hours, and can do nothing else. It asks for two permissions, shows no warning when you install it, and cannot read the pages it …

2026-10-29 UberDDR4 Under Bazel: An Open DDR4 Controller, Checked by One Command #FPGA #bazel #Vivado

UberDDR4 is an open-source DDR4 SDRAM controller and PHY for FPGAs, written by Angelo C. Jacobo. It connects a Wishbone master to DDR4 memory. It handles initialization, command timing, bank scheduling, refresh and PHY …

2026-10-28 Hardware Development with Bazel: the book is out #books #bazel #fpga

My book Hardware Development with Bazel: Authoring HDL Rules came out on 27 October 2026, in paperback and for Kindle. It has 334 pages. It teaches you to write Bazel rules for hardware: VHDL simulators, verification …

Reproducible Hardware and Build Engineering