TxHDL is a hardware description language that is a Rust library: a design is async Rust, where waiting for a clock edge is an .await and a transaction is a send on a channel. The book teaches it to hardware engineers who know Verilog or VHDL and to Rust programmers new to hardware, from a blinking LED through simulation, lowering to Verilog and VHDL, and formal checks. It ends with Vreteno, a RISC-V core written in TxHDL, running on an Artix-7 board and taken through an open ASIC flow.

Planned for 1 December 2026, in paperback and as an ebook. The language itself is on GitHub.