Vreteno RISC-V conformance

The RISC-V architectural tests on the Vreteno RV32IMAC core, run on 2026-10-07. Read the full report (PDF).

155 / 156tests pass on the netlist

156 / 156pass their self-check on Sail

1known failures, each with an issue

28,308results checked against Sail

4.96cycles per instruction

Failures

`SvSm_sv_mstatus_tvm_test-00` known failure

Tracked as https://git.hdlfactory.com/HDL/txhdl/issues/1347.

RVCP-SUMMARY: TEST FAILED - Test File "SvSm_sv_mstatus_tvm_test-00.S"

RVCP: DEBUG INFORMATION FOLLOWS
RVCP: Test Info: "test: 1; cg: SvSm_cg; cp: cp_satp_access; bin: tvm"
RVCP: Instruction: 0x30002773
RVCP: Approximate address (failure may be slightly after this): 0x40000048
RVCP: Register: x14
RVCP: Bad Value:      0x00001800
RVCP: Expected Value: 0x00101800
RVCP: END OF DEBUG INFORMATION

By suite

Suite	Tests	Sail	Netlist	Checks	Cycles per instruction
`ExceptionsSv`	2	2	2	108	4.20
`ExceptionsSvSm`	4	4	4	920	3.71
`ExceptionsSvZaamo`	2	2	2	44	4.22
`ExceptionsSvZaamoSm`	3	3	3	262	3.66
`ExceptionsSvZalrsc`	2	2	2	76	4.18
`ExceptionsSvZalrscSm`	3	3	3	518	3.62
`I`	39	39	39	10,176	5.54
`M`	8	8	8	3,184	6.97
`Sv`	25	25	25	1,016	4.25
`SvSm`	6	6	5	88	3.96
`Svbare`	2	2	2	20	4.27
`SvbareSm`	1	1	1	14	4.28
`Zaamo`	9	9	9	4,890	5.87
`Zalrsc`	2	2	2	648	4.34
`Zca`	26	26	26	3,600	4.98
`Zicntr`	2	2	2	20	4.31
`Zicsr`	6	6	6	1,068	5.17
`Zifencei`	1	1	1	10	5.58
`Zihintntl`	4	4	4	24	4.26
`ZihintntlZca`	4	4	4	24	4.24
`Zihintpause`	1	1	1	6	4.26
`Zmmul`	4	4	4	1,592	6.09

Every test

Test	Sail	Netlist	Checks	Cycles	Instructions
`ExceptionsSv_sv32_exceptions_Smode-00`	pass	pass	54	21,440	5,048
`ExceptionsSv_sv32_exceptions_Umode-00`	pass	pass	54	24,331	5,840
`ExceptionsSvSm_sv32_exceptions_mprv_S_Mmode-00`	pass	pass	222	45,006	11,405
`ExceptionsSvSm_sv32_exceptions_mprv_U_Mmode-00`	pass	pass	222	43,377	11,149
`ExceptionsSvSm_sv32_medeleg_Smode-00`	pass	pass	238	61,273	17,326
`ExceptionsSvSm_sv32_medeleg_Umode-00`	pass	pass	238	61,085	16,974
`ExceptionsSvZaamo_sv32_exceptions_Zaamo_Smode-00`	pass	pass	22	18,007	4,215
`ExceptionsSvZaamo_sv32_exceptions_Zaamo_Umode-00`	pass	pass	22	20,871	5,007
`ExceptionsSvZaamoSm_sv32_exceptions_Zaamo_mprv_S_Mmode-00`	pass	pass	98	31,287	7,858
`ExceptionsSvZaamoSm_sv32_medeleg_Zaamo_Smode-00`	pass	pass	82	46,714	13,277
`ExceptionsSvZaamoSm_sv32_medeleg_Zaamo_Umode-00`	pass	pass	82	46,526	12,925
`ExceptionsSvZalrsc_sv32_exceptions_Zalrsc_Smode-00`	pass	pass	38	19,892	4,707
`ExceptionsSvZalrsc_sv32_exceptions_Zalrsc_Umode-00`	pass	pass	38	22,792	5,507
`ExceptionsSvZalrscSm_sv32_exceptions_Zalrsc_mprv_S_Mmode-00`	pass	pass	194	40,966	10,718
`ExceptionsSvZalrscSm_sv32_medeleg_Zalrsc_Smode-00`	pass	pass	162	54,583	15,512
`ExceptionsSvZalrscSm_sv32_medeleg_Zalrsc_Umode-00`	pass	pass	162	54,395	15,160
`I-add-00`	pass	pass	398	38,877	6,435
`I-addi-00`	pass	pass	374	32,012	5,492
`I-and-00`	pass	pass	398	38,944	6,451
`I-andi-00`	pass	pass	374	32,014	5,492
`I-auipc-00`	pass	pass	62	16,153	3,516
`I-beq-00`	pass	pass	270	40,150	6,781
`I-bge-00`	pass	pass	270	40,539	6,805
`I-bgeu-00`	pass	pass	270	40,593	6,814
`I-blt-00`	pass	pass	270	41,044	6,817
`I-bltu-00`	pass	pass	270	40,896	6,824
`I-bne-00`	pass	pass	270	41,822	6,845
`I-fence-00`	pass	pass	6	15,296	3,548
`I-jal-00`	pass	pass	114	84,997	19,304
`I-jalr-00`	pass	pass	242	32,613	6,235
`I-lb-00`	pass	pass	130	20,825	4,149
`I-lbu-00`	pass	pass	130	20,847	4,158
`I-lh-00`	pass	pass	126	20,348	4,065
`I-lhu-00`	pass	pass	126	20,372	4,074
`I-lui-00`	pass	pass	62	16,105	3,498
`I-lw-00`	pass	pass	126	20,120	4,023
`I-nop-00`	pass	pass	6	14,008	3,251
`I-or-00`	pass	pass	398	38,889	6,434
`I-ori-00`	pass	pass	374	31,989	5,483
`I-sb-00`	pass	pass	210	21,998	4,397
`I-sh-00`	pass	pass	202	21,588	4,349
`I-sll-00`	pass	pass	398	38,878	6,435
`I-slli-00`	pass	pass	202	23,754	4,474
`I-slt-00`	pass	pass	394	38,642	6,407
`I-slti-00`	pass	pass	370	31,923	5,482
`I-sltiu-00`	pass	pass	370	31,949	5,491
`I-sltu-00`	pass	pass	394	38,697	6,424
`I-sra-00`	pass	pass	398	38,878	6,435
`I-srai-00`	pass	pass	202	23,756	4,474
`I-srl-00`	pass	pass	398	38,909	6,443
`I-srli-00`	pass	pass	202	23,755	4,474
`I-sub-00`	pass	pass	398	38,913	6,443
`I-sw-00`	pass	pass	200	21,409	4,329
`I-xor-00`	pass	pass	398	38,906	6,443
`I-xori-00`	pass	pass	374	32,015	5,492
`M-div-00`	pass	pass	398	50,474	6,443
`M-divu-00`	pass	pass	398	50,533	6,452
`M-mul-00`	pass	pass	398	39,430	6,451
`M-mulh-00`	pass	pass	398	39,422	6,452
`M-mulhsu-00`	pass	pass	398	39,517	6,478
`M-mulhu-00`	pass	pass	398	39,455	6,461
`M-rem-00`	pass	pass	398	50,542	6,443
`M-remu-00`	pass	pass	398	50,512	6,444
`Sv_sv32_VA_all_ones_Smode-00`	pass	pass	6	15,029	3,511
`Sv_sv32_VA_all_zeros_Smode-00`	pass	pass	6	15,054	3,522
`Sv_sv32_global_pte_Smode-00`	pass	pass	18	15,661	3,574
`Sv_sv32_global_pte_Umode-00`	pass	pass	18	18,606	4,358
`Sv_sv32_invalid_pte_Smode-00`	pass	pass	34	18,865	4,395
`Sv_sv32_invalid_pte_Umode-00`	pass	pass	34	20,404	4,791
`Sv_sv32_misaligned_page_Smode-00`	pass	pass	18	16,856	3,909
`Sv_sv32_misaligned_page_Umode-00`	pass	pass	18	17,742	4,111
`Sv_sv32_mstatus_mxr_Smode-00`	pass	pass	42	19,841	4,583
`Sv_sv32_mstatus_mxr_Umode-00`	pass	pass	42	22,753	5,367
`Sv_sv32_nleaf_pte_DAU_Smode-00`	pass	pass	5	14,078	3,296
`Sv_sv32_nleaf_pte_DAU_Umode-00`	pass	pass	5	14,078	3,296
`Sv_sv32_nleaf_pte_level0_Smode-00`	pass	pass	18	16,979	3,934
`Sv_sv32_nleaf_pte_level0_Umode-00`	pass	pass	18	17,860	4,136
`Sv_sv32_pte_reserved_rwx_Smode-00`	pass	pass	6	14,153	3,323
`Sv_sv32_pte_reserved_rwx_Umode-00`	pass	pass	6	14,153	3,323
`Sv_sv32_pte_rsw_Smode-00`	pass	pass	30	17,376	3,861
`Sv_sv32_pte_rsw_Umode-00`	pass	pass	30	21,655	5,049
`Sv_sv32_satp_access_Smode-00`	pass	pass	30	17,549	4,037
`Sv_sv32_spage_Smode-00`	pass	pass	82	25,431	5,813
`Sv_sv32_spage_access_Umode-00`	pass	pass	154	41,993	10,496
`Sv_sv32_spage_mstatus_sum_set_Smode-00`	pass	pass	54	21,974	5,093
`Sv_sv32_upage_Umode-00`	pass	pass	82	32,254	7,793
`Sv_sv32_upage_mstatus_sum_set_Smode-00`	pass	pass	106	28,890	6,781
`Sv_sv32_upage_mstatus_sum_unset_Smode-00`	pass	pass	154	35,413	8,615
`SvSm_sv32_mstatus_mprv_Smode-00`	pass	pass	10	14,890	3,478
`SvSm_sv32_mstatus_mprv_Umode-00`	pass	pass	10	14,847	3,470
`SvSm_sv32_satp_access_Mmode-00`	pass	pass	6	13,622	3,207
`SvSm_sv32_upage_mprv_set_sum_set_Smode-00`	pass	pass	10	15,175	3,576
`SvSm_sv32_upage_mprv_set_sum_unset_Smode-00`	pass	pass	26	17,532	4,246
`SvSm_sv_mstatus_tvm_test-00`	pass	known failure	26	21,438	6,649
`Svbare_Svbare_Smode-00`	pass	pass	10	13,863	3,255
`Svbare_Svbare_Umode-00`	pass	pass	10	14,634	3,419
`SvbareSm_Svbare_mstatus_mprv-00`	pass	pass	14	14,049	3,284
`Zaamo-amoadd.w-00`	pass	pass	490	58,919	10,146
`Zaamo-amoand.w-00`	pass	pass	490	58,909	10,146
`Zaamo-amomax.w-00`	pass	pass	610	69,461	11,706
`Zaamo-amomaxu.w-00`	pass	pass	610	69,488	11,715
`Zaamo-amomin.w-00`	pass	pass	610	69,465	11,706
`Zaamo-amominu.w-00`	pass	pass	610	69,487	11,715
`Zaamo-amoor.w-00`	pass	pass	490	58,887	10,137
`Zaamo-amoswap.w-00`	pass	pass	490	58,940	10,155
`Zaamo-amoxor.w-00`	pass	pass	490	58,912	10,146
`Zalrsc-lr.w-00`	pass	pass	106	19,132	3,933
`Zalrsc-sc.w-00`	pass	pass	542	125,744	29,479
`Zca-c.add-00`	pass	pass	298	31,707	5,652
`Zca-c.addi-00`	pass	pass	222	24,283	4,616
`Zca-c.addi16sp-00`	pass	pass	66	17,446	3,711
`Zca-c.addi4spn-00`	pass	pass	266	27,646	4,911
`Zca-c.and-00`	pass	pass	198	25,627	4,823
`Zca-c.andi-00`	pass	pass	182	22,228	4,352
`Zca-c.beqz-00`	pass	pass	42	16,340	3,575
`Zca-c.bnez-00`	pass	pass	42	16,343	3,557
`Zca-c.j-00`	pass	pass	46	30,477	6,790
`Zca-c.jal-00`	pass	pass	46	30,527	6,808
`Zca-c.jalr-00`	pass	pass	78	18,931	4,007
`Zca-c.jr-00`	pass	pass	46	18,572	4,074
`Zca-c.li-00`	pass	pass	114	20,246	3,934
`Zca-c.lui-00`	pass	pass	110	19,798	3,924
`Zca-c.lw-00`	pass	pass	66	16,939	3,645
`Zca-c.lwsp-00`	pass	pass	106	19,035	4,009
`Zca-c.mv-00`	pass	pass	142	22,304	4,398
`Zca-c.nop-00`	pass	pass	6	14,397	3,351
`Zca-c.or-00`	pass	pass	198	25,602	4,814
`Zca-c.slli-00`	pass	pass	210	24,491	4,537
`Zca-c.srai-00`	pass	pass	186	22,550	4,394
`Zca-c.srli-00`	pass	pass	186	22,550	4,394
`Zca-c.sub-00`	pass	pass	198	25,627	4,823
`Zca-c.sw-00`	pass	pass	126	18,296	3,939
`Zca-c.swsp-00`	pass	pass	222	21,161	4,279
`Zca-c.xor-00`	pass	pass	198	25,627	4,823
`Zicntr-csrrc-00`	pass	pass	10	14,625	3,392
`Zicntr-csrrs-00`	pass	pass	10	14,625	3,392
`Zicsr-csrrc-00`	pass	pass	222	24,569	4,584
`Zicsr-csrrci-00`	pass	pass	134	19,145	3,873
`Zicsr-csrrs-00`	pass	pass	222	24,532	4,576
`Zicsr-csrrsi-00`	pass	pass	134	19,145	3,873
`Zicsr-csrrw-00`	pass	pass	222	24,541	4,576
`Zicsr-csrrwi-00`	pass	pass	134	19,142	3,873
`Zifencei-fence.i-00`	pass	pass	10	19,180	3,439
`Zihintntl-ntl.all-00`	pass	pass	6	14,308	3,359
`Zihintntl-ntl.p1-00`	pass	pass	6	14,283	3,350
`Zihintntl-ntl.pall-00`	pass	pass	6	14,333	3,368
`Zihintntl-ntl.s1-00`	pass	pass	6	14,283	3,350
`ZihintntlZca-c.ntl.all-00`	pass	pass	6	14,434	3,405
`ZihintntlZca-c.ntl.p1-00`	pass	pass	6	14,409	3,396
`ZihintntlZca-c.ntl.pall-00`	pass	pass	6	14,459	3,414
`ZihintntlZca-c.ntl.s1-00`	pass	pass	6	14,409	3,396
`Zihintpause-pause-00`	pass	pass	6	14,308	3,359
`Zmmul-mul-00`	pass	pass	398	39,530	6,487
`Zmmul-mulh-00`	pass	pass	398	39,522	6,488
`Zmmul-mulhsu-00`	pass	pass	398	39,617	6,514
`Zmmul-mulhu-00`	pass	pass	398	39,555	6,497

How this was run

Core: Vreteno, TxHDL 662c01333a16
Tests: riscv-arch-test (ACT4) a215271eab12; 156 of 1028 tests apply
Reference: Sail RISC-V model 0.15
Compiler: riscv-none-elf-gcc (xPack GNU RISC-V Embedded GCC x86_64) 15.2.0
Simulator: Verilator, on the netlist TxHDL writes
Extensions: I, M, Zmmul, A, Zaamo, Zalrsc, C, Zca, Zicsr, Zifencei, Zicntr, Zihintpause, Zihintntl, Sm, S, U, Sv32, Svbare, Svade
Left out: Svade: the suite writes menvcfgh, which a privileged 1.11 core does not have (https://git.hdlfactory.com/HDL/txhdl/issues/1348)
Harness: 9c7dd19dd40c