This report runs RISC-V International’s architectural tests on Vreteno. The Sail reference model computes the result each test must reproduce, and each test runs on the core’s Verilog netlist under Verilator.

In the first run, 155 of the 156 tests that apply to the core passed. The one failure found a real defect: the core cannot set mstatus.TVM. The report is rebuilt every day against the newest commit of TxHDL, so the latest copy always describes the core as it is now.