RISC-V

• 2026-10-20 Bazelizing Third-Party FPGA Designs: Two Case Studies #FPGA#bazel#openxc7

  Converting existing open-source FPGA projects to Bazel and rules_openxc7 makes hardware builds reproducible, eliminates machine-specific paths, and enables one-command bitstream generation without vendor licensing …

• 2026-10-17 Bazelizing mmRISC-2: A Full RISC-V SoC with rules_openxc7 #FPGA#bazel#openxc7

  Converting existing open-source FPGA projects to Bazel and rules_openxc7 transforms fragile, vendor-locked hardware build scripts into reproducible, sandboxed workflows. This case study examines our complete Bazelization …

• 2026-10-15 rules_fusesoc: FuseSoC Cores as Bazel Dependencies #bazel#FPGA#RISC-V

  rules_fusesoc integrates FuseSoC, the FPGA core package manager, into hermetic Bazel builds. Users declare desired core libraries and IP dependencies in Bazel build files. The module resolves dependencies and exports …

• 2026-10-08 Doom on a RISC-V core written in TxHDL #TxHDL#FPGA#RISC-V

  Doom now runs on Vreteno, the RISC-V core written in TxHDL, on an Artix-7 FPGA board. The game draws into a framebuffer in DDR3 memory, the board shows it on HDMI, and the keys come over the serial line. This post shows …

• 2026-10-08 openxc7 or Vivado: Build Times and Results Measured #bazel#FPGA#openxc7

  I built the same three designs with the open toolchain and with Vivado, through the same Bazel rules, and timed every build from cold and warm caches. Small designs build two to three times faster with the open tools. …

• 2026-10-05 Linux boots to a shell on Vreteno #RISC-V#Linux#FPGA

  Mainline Linux now boots to a shell on Vreteno, the RISC-V core written in TxHDL. It runs on the Alinx AX7A200B board, an Artix-7 FPGA with 1 GiB of DDR3 memory, at 100 MHz. The kernel runs in supervisor mode with …

• 2026-09-29 Vreteno: a RISC-V core written in TxHDL #RISC-V#FPGA#Rust

  Vreteno is a 32-bit RISC-V processor core designed in TxHDL. TxHDL is a hardware description language implemented as a native Rust library. The core implements the RV32IMC instruction set architecture: the base integer …

• 2026-09-24 grlib: Gaisler’s GRLIB and the NOEL-V Core as a Bazel Module #bazel#FPGA#RISC-V

  The grlib Bazel module packages GRLIB, Gaisler’s (Frontgrade’s) GPL VHDL IP library, so that the NOEL-V RV64 RISC-V core and the AMBA infrastructure around it can be consumed as ordinary Bazel dependencies. It is the …

• 2026-09-20 An icosahedron on HDMI, drawn by a TxHDL core #TxHDL#FPGA#RISC-V

  tl;dr: A RISC-V core written in TxHDL draws a turning icosahedron on a monitor, with the TxHDL logo in the corner. Watch it at https://youtu.be/YbHtntvvydk. The whole thing, core, memory, video, Ethernet and a serial …

• 2026-09-12 TxHDL: a hardware description language is just a Rust async runtime #Rust#FPGA#RISC-V

  TxHDL is an open-source hardware description language embedded directly in Rust as an async runtime library, developed by Dragiša Janković and Filip Filmar (me). Instead of inventing a custom compiler and type checker, …

• 2026-09-03 rules_vivado: FPGA Synthesis and Place-and-Route in Bazel #bazel#FPGA#Vivado

  rules_vivado drives the AMD/Xilinx Vivado FPGA toolchain from Bazel: compile, simulate, synthesize, place-and-route, generate a bitstream, and program the device, all as ordinary build actions instead of clicks in a GUI …

• 2026-08-17 Bazel all the way down: how I build programmable hardware #bazel#FPGA#HER

  This is a description of how I build programmable hardware. Everything that goes into Cocoapuffs (my RISC-V system-on-chip on an Artix-7 FPGA), including the RTL, firmware, simulations, synthesis, bitstream, and board …

• 2026-07-19 Booting Fuchsia’s Zircon on a homebrew RISC-V SoC, on an Artix-7 FPGA #FPGA#RISC-V#Zircon

  Fuchsia’s Zircon kernel now boots on Cocoapuffs, my homebrew RISC-V system-on-chip on an AMD Artix-7 FPGA. As far as I know, this is the first Fuchsia boot on programmable hardware. Below you will find the boot video and …

• 2024-10-05 From zero to RISC-V in hardware, in 6 minutes #FPGA#bazel#Xilinx

  From zero to RISC-V in hardware, in 6 minutes Program your FPGA with a one-liner command. It’s a kind of magic. This is a project in sustainable FPGA development that I have been working on. It ties together several …

• 2024-08-31 bazel rules for a riscv64 bare metal rust compiler #Rust#bazel#RISC-V

  bazel rules for a riscv64 bare metal rust compiler This article assumes that you have bazel installed via the bazelisk method. This is the latest example in my repository at: https://github.com/filmil/bazel-experiments …

• 2024-08-17 bazel rules for a riscv64 bare metal GCC compiler #gcc#bazel#RISC-V

  bazel rules for a riscv64 bare metal GCC compiler The repository https://github.com/filmil/bazel_rules_gcc_riscv64_baremetal contains bazel rules that can be used for a hermetic bare metal GCC cross-compiler for a 64-bit …