RISC-V

• 2026-09-12 TxHDL: a hardware description language that is a Rust library #Rust#FPGA#RISC-V

  For the past while, Dragiša Janković and I have been working on a hardware description language (HDL). Why? you ask? We were worried about the fact that the mainstream HDLs seemed too low level (hi, Verilog!) to answer …

• 2026-09-03 rules_vivado: FPGA Synthesis and Place-and-Route in Bazel #bazel#FPGA#Vivado

  rules_vivado drives the AMD/Xilinx Vivado FPGA toolchain from Bazel: compile, simulate, synthesize, place-and-route, generate a bitstream, and program the device, all as ordinary build actions instead of clicks in a GUI …

• 2026-07-19 Booting Fuchsia’s Zircon on a homebrew RISC-V SoC, on an Artix-7 FPGA #FPGA#RISC-V#Zircon

  Fuchsia’s Zircon kernel now boots on Cocoapuffs, my homebrew RISC-V system-on-chip on an AMD Artix-7 FPGA: as far as I know, the first Fuchsia boot on programmable hardware. The boot video and the full chain, from a SERV …