EDA

• 2026-10-15 rules_fusesoc: FuseSoC Cores as Bazel Dependencies #bazel#FPGA#RISC-V

  rules_fusesoc integrates FuseSoC, the FPGA core package manager, into hermetic Bazel builds. Users declare desired core libraries and IP dependencies in Bazel build files. The module resolves dependencies and exports …

• 2026-10-08 openxc7 or Vivado: Build Times and Results Measured #bazel#FPGA#openxc7

  I built the same three designs with the open toolchain and with Vivado, through the same Bazel rules, and timed every build from cold and warm caches. Small designs build two to three times faster with the open tools. …

• 2026-09-29 wdbcvt: Bundling Waveform Test Corpora and Daily Nightly Releases #EDA#Vivado#bazel

  wdbcvt now publishes two new release archives with every build: a documentation bundle and a waveform corpus. The waveform archive packages the test suite’s .wdb files, ground-truth .fst conversions, and HDL source files …

• 2026-09-24 grlib: Gaisler’s GRLIB and the NOEL-V Core as a Bazel Module #bazel#FPGA#RISC-V

  The grlib Bazel module packages GRLIB, Gaisler’s (Frontgrade’s) GPL VHDL IP library, so that the NOEL-V RV64 RISC-V core and the AMBA infrastructure around it can be consumed as ordinary Bazel dependencies. It is the …

• 2026-09-12 Automated Tests on Simulation Output, with SQLite #EDA#VHDL#Verilog

  This article demonstrates converting a VCD dump into an indexed SQLite database using go-vcd-parser, then using a query language to answer questions about the signals. A logic simulator answers questions about a digital …

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  2026-09-04 wdbcvt: reading Vivado’s undocumented .wdb waveform files #EDA#Vivado#FPGA

  wdbcvt is an open-source converter that reads Vivado’s .wdb waveform files and converts them to the open-source FST format. Vivado’s xsim simulator writes simulation waveforms to a proprietary binary format that external …

• 2026-09-03 rules_vivado: FPGA Synthesis and Place-and-Route in Bazel #bazel#FPGA#Vivado

  rules_vivado drives the AMD/Xilinx Vivado FPGA toolchain from Bazel: compile, simulate, synthesize, place-and-route, generate a bitstream, and program the device, all as ordinary build actions instead of clicks in a GUI …

• 2026-08-17 Bazel all the way down: how I build programmable hardware #bazel#FPGA#HER

  This is a description of how I build programmable hardware. Everything that goes into Cocoapuffs (my RISC-V system-on-chip on an Artix-7 FPGA), including the RTL, firmware, simulations, synthesis, bitstream, and board …

• 2026-02-01 Inventory of programmable hardware tooling #bazel#FPGA#Vivado

  A link page of interesting libraries and utilities I found. Libraries, utilities, etc. https://registry.bazel.build/modules/rules_verilator https://github.com/lromor/fpga-assembler …

• 2025-09-01 Writing XDC Clock Constraints for Vivado #FPGA#Vivado#EDA

  Writing XDC Clock Constraints for Vivado This guide explains how to properly constrain a digital design with multiple clocks in an XDC (Xilinx Design Constraints) file, specifically for use in Vivado batch mode. We’ll …

• 2025-07-14 Mastering Resolved Signals in VHDL: A Comprehensive Guide for Digital Design #EDA#VHDL#FPGA

  I asked Gemini to teach me about the VHDL resolved signals. What you read below is the result. Mastering Resolved Signals in VHDL: A Comprehensive Guide for Digital Design 1. Introduction to Signals in VHDL The …

• 2025-07-07 How to shoot yourself in the foot with inout signals #EDA#VHDL#FPGA

  How to shoot yourself in the foot with inout signals They say that no good deed goes unpunished. Here’s an example of a footgun in VHDL which stems from in my view an eminently reasonable desire to keep the entity …

• 2025-06-29 VHDL IEEE Libraries and Numeric Type Conversion: A Definitive Reference #EDA#VHDL#FPGA

  I asked Gemini to teach me the VHDL type conversions. What you read below is the result. An annoying generated podcast will be available for a while. VHDL IEEE Libraries and Numeric Type Conversions: A Definitive …

• 2025-06-19 Packaging AMD Xilinx Vivado ML Standard edition 2025.1 in a Docker container #Xilinx#FPGA#Docker

  I updated the repository https://github.com/filmil/vivado-docker/ with the changes required to package Vivado 2025.1. As of this writing, version 2025.1 is the last published version. I hope that the updated version will …

• 2024-11-16 Using glbl.v module in a Verilog simulation in Vivado #FPGA#Vivado#Xilinx

  A quick note about correct use of glbl.v in a Verilog simulation in Vivado. This note is way less confusing than any notes you may find elsewhere on the Internet. glbl.v is a small collection of “global” signals that are …

• 2024-10-26 go-vcd-parser: a tested VCD parser and toolkit in Go #EDA#Verilog#VHDL

  go-vcd-parser reads Value Change Dump (VCD) files, the waveform format that simulators such as Verilator, Icarus Verilog and nvc write. The format is defined in IEEE 1800. The parser handles the 4-value format and the …

• 2024-10-05 From zero to RISC-V in hardware, in 6 minutes #FPGA#bazel#Xilinx

  From zero to RISC-V in hardware, in 6 minutes Program your FPGA with a one-liner command. It’s a kind of magic. This is a project in sustainable FPGA development that I have been working on. It ties together several …

• 2024-09-03 bazel rules for GHDL #bazel#VHDL#EDA

  bazel rules for GHDL I present to you https://github.com/filmil/bazel_rules_ghdl: a set of bazel rules for converting VHDL into Verilog. This for example allows running VHDL code in a Verilator simulation. Commercial …

• 2024-07-08 Remote programming of an AMD (fka Xilinx) Artix-7 device #FPGA#Vivado#Xilinx

  Summary Here is how you can set up a hardware server (hw_server) in AMD Vivado 2023.2. Once you do this, that you can move your workbench to a virtual machine in your cloud of choice - mine is GCP - but program a device …

• 2023-11-20 Packaging AMD Xilinx Vivado ML Standard edition in a Docker container #Xilinx#FPGA#Docker

  A while back I wanted to make a hermetic environment for repeatably running Docker tooling. The results are here: https://github.com/filmil/vivado-docker/ At this time, it’s only able to run the GUI version of the tool. …