Verilog

• 2026-10-20 Bazelizing Third-Party FPGA Designs: Two Case Studies #FPGA#bazel#openxc7

  Converting existing open-source FPGA projects to Bazel and rules_openxc7 makes hardware builds reproducible, eliminates machine-specific paths, and enables one-command bitstream generation without vendor licensing …

• 2026-10-17 Bazelizing a Custom RISC CPU with 4x4 Systolic Matrix Accelerator #FPGA#bazel#openxc7

  Open-source digital signal processing and machine learning accelerators are frequently published as student or research projects. While the RTL architecture is often innovative, the surrounding build and test scaffolding …

• 2026-10-14 First Steps with rules_openxc7: A Beginner’s Guide #bazel#FPGA#openxc7

  This tutorial teaches you how to build your first FPGA bitstream with Bazel and the open-source rules_openxc7 toolchain. You do not need any prior Bazel experience, and you do not need to install AMD Vivado or compile …

• 2026-09-12 Automated Tests on Simulation Output, with SQLite #EDA#VHDL#Verilog

  This article demonstrates converting a VCD dump into an indexed SQLite database using go-vcd-parser, then using a query language to answer questions about the signals. A logic simulator answers questions about a digital …

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  2026-09-04 wdbcvt: reading Vivado’s undocumented .wdb waveform files #EDA#Vivado#FPGA

  wdbcvt is an open-source converter that reads Vivado’s .wdb waveform files and converts them to the open-source FST format. Vivado’s xsim simulator writes simulation waveforms to a proprietary binary format that external …

• 2024-11-16 Using glbl.v module in a Verilog simulation in Vivado #FPGA#Vivado#Xilinx

  A quick note about correct use of glbl.v in a Verilog simulation in Vivado. This note is way less confusing than any notes you may find elsewhere on the Internet. glbl.v is a small collection of “global” signals that are …

• 2024-10-26 go-vcd-parser: a tested VCD parser and toolkit in Go #EDA#Verilog#VHDL

  go-vcd-parser reads Value Change Dump (VCD) files, the waveform format that simulators such as Verilator, Icarus Verilog and nvc write. The format is defined in IEEE 1800. The parser handles the 4-value format and the …

• 2024-10-07 How to use $readmemh correctly #FPGA#Verilog

  What? $readmemh is a Verilog directive that allows you to initialize an array. It works differently in simulation compared to synthesis. In simulation, this directive behaves as a “read file into array”. In synthesis, …