ArtyA7

• 2026-10-17 Bazelizing a Custom RISC CPU with 4x4 Systolic Matrix Accelerator #FPGA#bazel#openxc7

  Open-source digital signal processing and machine learning accelerators are frequently published as student or research projects. While the RTL architecture is often innovative, the surrounding build and test scaffolding …

• 2026-10-17 Bazelizing mmRISC-2: A Full RISC-V SoC with rules_openxc7 #FPGA#bazel#openxc7

  Converting existing open-source FPGA projects to Bazel and rules_openxc7 transforms fragile, vendor-locked hardware build scripts into reproducible, sandboxed workflows. This case study examines our complete Bazelization …