Hardware teams build FPGA and ASIC designs with scripts that cannot tell what really needs to rebuild, and cannot reproduce last year’s bitstream on a new machine. This book shows how to build hardware with Bazel, so builds are fast and correct, as they are for software. It teaches Bazel rule authoring for VHDL simulators, verification frameworks and AMD Vivado from real, published rulesets, up to complete verification and RTL-to-bitstream flows.

Planned for 1 November 2026, in paperback and for Kindle. The companion code is public now.