Vivado

A link page of interesting libraries and utilities I found.

This guide explains how to properly constrain a digital design with multiple clocks in an XDC (Xilinx Design Constraints) file, specifically for use in Vivado batch mode. We’ll cover primary clocks, generated clocks, and the relationships between them.

I updated the repository https://github.com/filmil/vivado-docker/ with the changes required to package Vivado 2025.1. As of this writing, version 2025.1 is the last published version. I hope that the updated version will remove some of the bugs I discovered in the previous version I dockerized, which was 2023.2.

A quick note about correct use of glbl.v in a Verilog simulation in Vivado. This note is way less confusing than any notes you may find elsewhere on the Internet.

Program your FPGA with a one-liner command. It’s a kind of magic.

Here is how you can set up a hardware server (hw_server) in AMD Vivado 2023.2.

A while back I wanted to make a hermetic environment for repeatably running Docker tooling.