All available at: https://hdlfactory.com/bazel-registry/ if you are willing to use bazel.
This guide explains how to properly constrain a digital design with multiple clocks in an XDC (Xilinx Design Constraints) file, specifically for use in Vivado batch mode. We’ll cover primary clocks, generated clocks, and the relationships between them.
I asked Gemini to teach me about the VHDL resolved signals. What you read below is the result.
They say that no good deed goes unpunished. Here’s an example of a footgun in VHDL which stems from in my view an eminently reasonable desire to keep the entity interface definitions compact.
I asked Gemini to teach me the VHDL type conversions. What you read below is the result. An annoying generated podcast will be available for a while.
I updated the repository https://github.com/filmil/vivado-docker/ with the changes required to package Vivado 2025.1. As of this writing, version 2025.1 is the last published version. I hope that the updated version will remove some of the bugs I discovered in the previous version I dockerized, which was 2023.2.
glbl.v module in a Verilog simulation in Vivado
A quick note about correct use of glbl.v in a Verilog simulation in Vivado. This note is way less confusing than any notes you may find elsewhere on the Internet.
$readmemh is a Verilog directive that allows you to initialize an array. It works differently in simulation compared to synthesis. In simulation, this directive behaves as a “read file into array”. In synthesis, this directive behaves as a repository of initial values for, say, block RAM.
Program your FPGA with a one-liner command. It’s a kind of magic.
Here is how you can set up a hardware server (hw_server) in AMD Vivado 2023.2, in such a way that you can move your workbench to a virtual machine in your cloud of choice - mine is GCP - but program a device which is attached to a machine that’s close to you.
A while back I wanted to make a hermetic environment for repeatably running Docker tooling.