I asked Gemini to teach me about the VHDL resolved signals. What you read below is the result.
They say that no good deed goes unpunished. Here’s an example of a footgun in VHDL which stems from in my view an eminently reasonable desire to keep the entity interface definitions compact.
I asked Gemini to teach me the VHDL type conversions. What you read below is the result. An annoying generated podcast will be available for a while.
I updated the repository https://github.com/filmil/vivado-docker/ with the changes required to package Vivado 2025.1. As of this writing, version 2025.1 is the last published version. I hope that the updated version will remove some of the bugs I discovered in the previous version I dockerized, which was 2023.2.
glbl.v module in a Verilog simulation in Vivado
A quick note about correct use of glbl.v in a Verilog simulation in Vivado. This note is way less confusing than any notes you may find elsewhere on the Internet.
Program your FPGA with a one-liner command. It’s a kind of magic.
bazel rules for GHDL
I present to you https://github.com/filmil/bazel_rules_ghdl: a set of bazel rules for converting VHDL into Verilog.
Here is how you can set up a hardware server (hw_server) in AMD Vivado 2023.2.
A while back I wanted to make a hermetic environment for repeatably running Docker tooling.